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Join our teamMPC8560ADS: Application Development System for MPC8560 ARCHIVED
MPC8560ADS Board Photo
Specifications
Technical and Functional Specifications
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Memory
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Connectivity
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| 256 kB I2C Boot EEPROM |
Documents and Software
Documents ( 6 )
Documents
Reference Manual ( 5 )
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PowerPC ™ e500 Core Family - Reference Manual (REV 1 )
The primary objective of this user’s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs).
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MPC8560/MPC8540 Power QUICC III ADS Board Users Guide (REV 0.6 )
This document defines a technical specification for the MPC8560/MPC8540 ADS; this development board will be used to verify the operation of the MPC8560 and MPC8540 integrated communications processors.
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Errata to the MPC8560 PowerQUICC® III Integrated Communications Processor Reference Manual, Rev. 1 (REV 1.4 )
This errata describes corrections to the MPC8560 reference manual, Rev. 1.
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MPC8560 Reference Manual (REV 1 )
MPC8560 PowerQUICC® III Integrated Communications Processor Reference Manual
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PowerPC e500 Application Binary Interface User's Guide (REV 1.0 )
e500 application binary interface user's guide
Application Note ( 1 )
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AN2665, e500 Software Optimization Guide (eSOG) - Application Notes (REV 0 )
AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations.