The primary objective of this user’s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs).

This document defines a technical specification for the MPC8560/MPC8540 ADS; this development board will be used to verify the operation of the MPC8560 and MPC8540 integrated communications processors.

This errata describes corrections to the MPC8560 reference manual, Rev. 1.

MPC8560 PowerQUICC^® III Integrated Communications Processor Reference Manual

e500 application binary interface user's guide

AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations.