MC92460: Multichannel HDLC Controller Peripheral ARCHIVED

Major features of the MC92460 include the following:

• Controllers
  • Maximum throughput of up to 2 Gbps; individual controllers operating up to 66.7 Mbps
  • All communication controllers operating in asynchronous mode
• HDLC Channels
  • 40 dedicated full-duplex HDLC channels
  • Each HDLC channel supporting a maximum of 66.7 Mbps
  • A default of 64 buffer descriptors per channel (32 TxBD + 32 RxBD) or 4096 total buffer descriptors
  • Configurable number of buffer descriptors in each channel (minimum of 0, maximum of 4096)
• Buffering
  • 32-Kbyte on-chip dual port RAM for buffer descriptors
  • A default of 64 buffer descriptors per channel (32 TxBD + 32 RxBD) or 4096 total buffer descriptors
  • 256 Kbits on-chip memory for data buffers
  • 256-Kbit communication buffer storing up to 819 bytes per frame
  • Maximum buffer length of 64 Kbytes
  • 80 channel virtual DMA functionality executing between off-chip memory and the communications buffer
• Framing
  • Programmable frame size (maximum 64 Kbytes)
  • Flexible buffers and multiple buffers per frame
  • Separate interrupts for frames and buffers (Tx and Rx)
  • Received frames threshold to reduce interrupt overhead
  • Flag/abort/idle generation and detection
  • Zero insertion and deletion
  • 16- or 32-bit CRC-CCITT generation and checking
  • Detection of non-connected aligned frames
  • Detection of too-long frames
  • Programmable flags (0-15) between successive frames
  • Automatic retransmission in case of collision
  • Echo and local loopback mode for testing
• Leader interface unit
  • Directly connects with 64-bit data, 32-bit address 60x bus
  • Supports 66MHz 60x bus speed
  • Virtual DMA supports an 80-channel HDLC leader
  • Virtual DMA functionality executing off-chip memory to internal memory
  • Either the leader or the follower MC92460 can be the 60x bus leader
  • Bus supports multi-leader design
  • Up to eight devices may be connected in parallel on the 60x bus
  • Supports single beat and burst accesses
• Baud rate generator (BRG)
  • 40 independent and identical baud rate generators, one per channel
  • On-chip PLL for configurable baud rate generation (maximum of 66.7 MHz)
  • A 16x divider option allows slow baud rates at high system frequencies
  • Each BGR output can be routed to a pin (TxCKn and RxCKn)
  • On-the-fly changes allowed
• 480-pin TBGA, 1.27mm pitch packaging
• Applications
  • Supports IEEE1149.1 JTAG controller standard
  • Separate power supplies for core (1.8V) and internal logic (3.3V)