UDA1355H: Stereo audio codec with SPDIF interface ARCHIVED

1.1 General

• 2.7 to 3.6 V power supply
• Integrated digital interpolator filter and Digital-to-Analog Converter (DAC)
• 24-bit data path in interpolator
• No analog post filtering required for DAC
• Integrated Analog-to-Digital Converter (ADC), Programmable Gain Amplifier (PGA) and digital decimator filter
• 24-bit data path in decimator
• Master or slave mode for digital audio data I/O interface
• I²S-bus, MSB-justified, LSB-justified 16, 18, 20, and 24 bits formats supported on digital I/O interface.

1.2 Control

• Controlled by means of static pins or microcontroller (L3-bus or I²C-bus) interface.

1.3 IEC 60958 input

• On-chip amplifier for converting IEC 60958 input to CMOS levels
• Supports level I, II and III timing
• Selectable IEC 60958 input channel, one of four
• Supports input frequencies from 28 to 96 kHz
• Lock indication signal available on pin LOCK
• 40 status bits can be read for left and right channel via L3-bus or I²C-bus
• Channel status bits available via L3-bus or I²C-bus: lock, pre-emphasis, audio sample frequency, two channel Pulse Code Modulation (PCM) indication and clock accuracy
• Pre-emphasis information of incoming IEC 60958 bitstream available in register
• Detection of digital data preamble, such as AC3, available on pin in microcontroller mode.

1.4 IEC 60958 output

• CMOS output level converted to IEC 60958 output signal
• Full-swing digital signal, with level II timing using crystal oscillator clock
• 32, 44.1 and 48 kHz output frequencies supported in static mode
• 32, 44.1 and 48 kHz output frequencies (including double and half of these frequencies) supported in microcontroller mode
• Via microcontroller, 40 status bits can be set for left and right channel.

1.5 Digital I/O interface

• Supports sampling frequencies from 16 to 100 kHz
• Supported static mode:
  • I²S-bus format
  • LSB-justified 16 and 24 bits format
  • MSB-justified format.
• Supported microcontroller mode:
  • I²S-bus format
  • LSB-justified 16, 18, 20 or 24 bits format
  • MSB-justified format.
• BCK and WS signals can be slave or master, depending on application mode.

1.6 ADC digital sound processing

• Supports sampling frequencies from 16 to 100 kHz
• Analog front-end includes a 0 to +24 dB PGA in steps of 3 dB, selectable via microcontroller interface
• Digital independent left and right volume control of +24 to -63.5 dB in steps of 0.5 dB via microcontroller interface
• Bitstream ADC operating at 64f_s
• Comb filter decreases sample rate from 64f_s to 8f_s
• Decimator filter (8f_s to f_s ) made of a cascade of three FIR half-band filters.

1.7 DAC digital sound processing

• Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio sampling frequencies
• Automatic de-emphasis when using IEC 60958 to DAC
• Soft mute made of a cosine roll-off circuit selectable via pin MUTE or L3-bus interface
• Programmable digital silence detector
• Interpolating filter (f_s to 64f_s or f_s to 128f_s ) comprising a recursive and a FIR filter in cascade
• Selectable fifth-order noise shaper operating at 64f_s or third-order noise shaper operating at 128f_s (specially for low sampling frequencies, e.g. 16 kHz) generating bitstream for DAC
• Filter Stream DAC (FSDAC)
• In microcontroller mode:
  • Left and right volume control (for balance control) 0 to-78 dB and -∞
  • Left and right bass boost and treble control
  • Optional resonant bass boost control
  • Mixing possibility of two data streams.