Analog Front End

Below is the nomenclature of the N-AFE family of devices:

The low-power flavor has a max data rate of 288 ksps while the high-speed version can support up to 576 ksps in Normal Settling mode.

Refer to the data sheet or contact an NXP sales representative for available part numbers.

The N-AFE has eight selectable PGA gain settings of 0.2 V/V to 16 V/V that provide eight differential input full-scale ranges from ±25 V to ±312.5 mV for a variety of applications. In general, all of the HV input characteristics are specified to the linear (nominal) input ranges for all of the channel gain settings, which is 80 % of the full input range.

Contrary to competitor solutions that implement two matched current generators to cancel the RTD wire resistance, the N-AFE utilizes the integrated current generator (VIEX) with low-temperature drift performance of 4 ppm/°C typical. The N-AFE optimizes the number of RTDs that can be connected to a single chip by using a single-current source allowing four 3-wire RTD measurements with a single chip.

The user calibration is the process by which the N-AFE is calibrated when it is already mounted on a PCB. The factory calibration is performed during chip manufacturing at the NXP factory. The user calibration achieves overall better accuracy with a typical TUE of ±0.002 % of full scale at room temperature. This is because all the errors introduced by external components and the soldering process are calibrated too. However, the accuracy guaranteed by the factory calibrated part, which is ±0.06 % of full scale at room, allows our customers to avoid the expensive and time-consuming calibration process if the provided accuracy fits their requirements.

The factory calibration is performed for all 8 PGA gain settings (input ranges) and the coefficients are stored in separate registers. Gain/OS coefficient pointer of 0, 1, 2, …, 7 should be used for Gain_code=0, 1, 2, …, 7 respectively for datasheet specified measurement accuracy. Please refer to Table 12 in the datasheet NAFE13388.

The N-AFE is available in both a low-power (LP) version and a high-speed (HS) version with maximum data rates of 288 ksps and 576 ksps respectively. The single-channel conversion with normal settling provides the fastest readout of 3.472 us for the LP (NAFE1x388) version and 1.738 us for the HS (NAFE7x388) version.

When in Multichannel Conversion mode, the ADC input signal path requires 16.4 us and 8.2 us front-end settling time (defined as Tswitch in the EC table) for NAFE1x388 and NAFE7x388 respectively. The user should use single-cycle settling for multichannel readout to avoid settling errors. The ADC data rate in single-cycle settling mode is a quarter of the data rate in Normal Settling mode, for example, 72 ksps and 144 ksps for LP and HS parts respectively.

Code 17 for channel programmable delay meets the Tswitch requirement in both the low-power and high-speed flavors.

n channel read time = n * (Tcnv + Tch_delay)
where n = number of channels in multichannel read mode.
Tcnv = 1/DataRate
Tch_delay ≥ Tswitch.

The fastest readout for 8 inputs in Multichannel Conversion mode with single-cycle settling is:

NAFE1x388's fastest eight-channel read time = 8 * (13.88 us + 16.49 us) ≈ 240 us …..30 us/channel

NAFE7x388's fastest eight-channel read time = 8 * (6.94 us + 8.24 us) ≈ 120 us……….15 us/channel

The NAFE13388 features a digital filter that provides a 50 Hz and 60 Hz Normal mode rejection (NMR) at lower data rates. The figure below shows the SINC4 filter NMR at the date rates of 10 sps, 50 sps and 60 sps.

The N-AFE provides more than 110 dB CMRR at data rates much higher than 60 sps (without 50/60 Hz rejection of notch filter) as shown in the figure below.

Static crosstalk: ±1 µV/V

Dynamic crosstalk (not AC spec): ±1 µV/V

Below are the test conditions for crosstalk parameters:

1. Input crosstalk DC (single channel):
   1. Set the target channel at 0 V and vary the main channel from 0 V to 10 V
   2. This test uses single-channel conversion to see the impact of the main channel on the target channel
   3. The above procedure is repeated for the main channel varying from 0 V to -10 V
2. Input crosstalk dynamic (multichannel not an AC crosstalk):
   1. Set the target channel to -10 V and the adjacent main channel from 0 V to 10 V
   2. This test uses multichannel conversion to see the impact of the main channel on the target channel
   3. This quantifies the effect of the channel path settling (MUX+PGA) at specified DR0 and CH_delay in condition for a worst-case input swing at the ADC input
   4. The above procedure is repeated for the target channel at 10 V and the adjacent main channel varying from 0 V to -10 V