IoT Gateway/Communication HUB


Block Diagram

IoT Gateway/Communication HUB

IoT Gateway/Communication HUB BD

Supported Devices

Security and Authentication


Wireless Connectivity


Processors and Microcontrollers

LPC54000 Arm Cortex-M4


NFC Readers


Arm Cortex-M4 core

  • Arm Cortex-M4 processor, running at a frequency of up to 180 MHz
  • Floating Point Unit (FPU) and Memory Protection Unit (MPU)
  • Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
  • Non-maskable Interrupt (NMI) input with a selection of sources
  • Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watchpoints. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter
  • System tick timer

On-chip memory

  • 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB traffic
  • General-purpose One-Time Programmable (OTP) memory for *AES keys and user application specific data
  • Up to 4 MB On-chip Flash**

ROM API support

  • In-Application Programming (IAP) and In-System Programming (ISP)
  • ROM-based USB drivers (HID, CDC, MSC, and DFU)
  • Booting from USART, SPI, I2C, USB0/1, EMC (static memory), and SPIFI (QSPI flash)
  • OTP API for programming OTP memory
  • Random Number Generator (RNG) API.*
  • AES API for programming AES memory.*


Quick reference to our documentation types.

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