JN5189/88 (T): High-Performance and Ultra-Low-Power MCUs for Zigbee® and Thread with Built-In NFC Option


Product Details

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Block Diagram

JN5189/88 Block Diagram

JN5189/88 Block Diagram


CPU and Memory

  • Up to 48 MHz Cortex-M4
  • Up to 640 KB flash, up to 152 kB RAM, 128 KB ROM
  • NFC NTAG Option with EEPROM
  • Quad-SPI for execute in place or data storage in NVM

RF performance/power consumption

  • -100 dBm RX sensitivity
  • up to 11dBm TX power
  • RX 4.3mA, DC/DC on at 3V
  • TX 7.4mA @ 0dBm, 20.3mA @ 10dBm
  • 2.4 GHz IEEE 802.15.4 compliant


  • AES256 with hardware protected key
  • Hash engine (SHA256)
  • Code readout protection

Digital and Analog Interfaces

  • UART/SPI/I2C up to 2
  • ISO7816 Interface for Secure Access Module
  • 8 ch 12-bit ADC,
  • 1 Analog comparator
  • Digital Microphone Interface and Audio Event Detection

Clocks and timers

  • 32 MHz and 32.768 kHz crystals
  • Low and High Frequency Internal Clock sources
  • 4 x general purpose timer
  • 32K sleep timer
  • Watchdog timer
  • RTC with calibration

Operating Conditions

  • Operating voltage: 1.9 to 3.6 V
  • Junction Temperature range: -40 to 125 °C


Quick reference to our documentation types.

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Design Resources

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Design Files

2 design files

  • Printed Circuit Boards and Schematics

    Coin Cell Hardware Design Files.

  • Design Files - miscellaneous

    JN-RD-6054-JN5189 Design Files


5 hardware offerings


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Note: For better experience, software downloads are recommended on desktop.


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