Smart Point of Sale


Block Diagram

Choose a diagram:

K12F Smart POS

Smart POS BD1

i.MX RT Smart POS

Smart POS BD2

Supported Devices

Analog and Mixed Signal

Real-Time Clocks

Voltage Level Translators

Processors and Microcontrollers

K2x / KS2x USB


NFC Readers

Security and Authentication

Contact Readers


  • 6468 CoreMark with Cortex®-M7 @ 1 GHz + Arm Cortex®-M4 @ 400 MHz
  • 2 MB SRAM with 512 KB of TCM for Cortex-M7 and 256 KB of TCM for Cortex-M4
  • Advanced security, including secure boot and crypto engines, and is part of the EdgeLock® Assurance program
  • 2 x Gb ENET with AVB and TSN
  • 2D GPU
  • Supported by MCUXpresso suite of software and tools
  • NFC Features
    • Host interfaces: SPI, I2C, UART
    • Up to 8 GPOs
    • 512 byte FIFO buffer
    • high-security reader using SAM interface
    • Maximum transmitter current: 350 mA operating with 500 mA limiting value
    • Freely programmable 6 kB EEPROM
    • Supply voltage: 2.5 to 5.5 V
    • Power-save modes: hard power-down, standby, extended LPCD options


Quick reference to our documentation types.

15 documents

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