Quad 6-Bit Multiplexed I²C-Bus EEPROM DIP Switch

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Block Diagram

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PCA9561 Block Diagram

PCA9561 Block Diagram

Block diagram: PCA9561D, PCA9561PW


  • Selection of non-volatile register_n as source to MUX_OUT pins via I²C-bus
  • I²C-bus can override MUX_SELECT pin in selecting output source
  • 6-bit 5-to-1 multiplexer DIP switch
  • Four internal non-volatile registers
  • Internal non-volatile registers programmable and readable via I²C-bus
  • Six open-drain multiplexed outputs
  • 400 kHz maximum clock frequency
  • Operating supply voltage 3.0 V to 3.6 V
  • 5 V and 2.5 V tolerant inputs/outputs
  • Useful for Speed Step configuration of laptop computer
  • Two address pins, allowing up to four devices on the I²C-bus
  • MUX_IN values readable via I²C-bus
  • ESD protection exceeds 200 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA


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Design Resources

Design Files

2 design files

  • Models

    PCA9561 IBIS model

  • Symbols and Footprints

    PCA9561PW-TSSOP20-CAD Symbol and PCB Footprint – BXL File

Engineering Services

2 engineering services

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