MPC603E: Host Processor ARCHIVED

The MPC603e microprocessor is a superscalar design capable of issuing three instructions per clock cycle into five independent execution units, including:

• Integer unit
• Load/Store unit
• Floating-point unit
• System register unit
• Branch processing unit

The ability to execute multiple instructions in parallel, to pipeline instructions , and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for MPC603e systems.

The MPC603e microprocessor features a low-power 2.5-volt or 3.3-volt design with three power-saving modes—doze, nap and sleep. These user-programmable modes progressively reduce the power drawn by the processor.

The MPC603e microprocessor also uses dynamic power management to selectively activate functional units as they are needed by the executing instructions. Unused functional units enter a low-power state automatically without affecting performance, software execution, or external hardware.

The MPC603e microprocessor has separate 16-Kbyte, physically-addressed instruction and data caches. Both caches are four-way set-associative. The MPC603e microprocessor also contains separate memory management units (MMUs) for instructions and data. The MMUs support 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Access privileges and memory protection are controlled on block or page granularities. Large, 64-entry translation lookaside buffers (TLBs) provide efficient physical address translation and support for demand virtual-memory management on both page- and variable-sized blocks.

The MPC603e microprocessor has a selectable 32- or 64-bit data bus and a 32-bit address bus. Support is included for burst, split and pipelined transactions. The interface provides snooping for data cache coherency. The MPC603e microprocessor maintains MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices.