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The MPC755 and MPC745 Host Processors are high-performance, low-power, 32-bit implementations of the Reduced Instruction Set Computer (RISC) architecture, specially enhanced for embedded applications.
MPC755 and MPC745 processors differ only in that the MPC755 features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The MPC755 is a drop-in replacement for the award winning MPC750 processor and is footprint and user software code compatible with the MPC7400 processor with AltiVec® ™ technology.
The MPC745 is a drop-in replacement for the MPC740 processor and is also footprint and user software code compatible with the MPC603e processor. MPC755/745 processors provide on-chip debug support and are fully JTAG-compliant.
Superscalar Microprocessor
MPC755 and MPC745 microprocessors are superscalar, capable of issuing three instructions per clock cycle (two instructions + branch) into six independent execution units:
The ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for MPC755 and MPC745 systems.
Power Management
The MPC755 and MPC745 microprocessors feature a low-power 2.0-volt design with three power-saving user-programmable modes—doze, nap and sleep—which progressively reduce the power drawn by the processor.
These low-power microprocessors offer dynamic power management to selectively activate functional units as they are needed by the executing instructions. Both microprocessors also provide a thermal assist unit and instruction cache throttling for software-controllable thermal management.
Cache and MMU Support
The MPC755/745 microprocessors have separate 32-Kbyte, physically-addressed instruction and data caches. Both caches can be locked in part or whole to provide storage of critical data, key performance algorithms, or code loops for fast response time. The MPC755 microprocessor's dedicated L2 cache interface with on-chip L2 tags (up to 1MB) features support for direct-mapped SRAM mode, physically-mapped SRAM mode, a fast (typically 1/2 core speed) interface to memory, instruction-only or data-only modes, and parity checking on both L2 address and data.
MPC755/745 microprocessors contain separate memory management units (MMUs) for instructions and data, supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Both feature eight instruction block address translation (iBAT) and eight data block address translation (dBAT) registers. Access privileges and memory protection are controlled on block or page granularities. Large, 128-entry translation lookaside buffers (TLBs) provide efficient physical address translation and support for virtual-memory management on both page- and variable-sized blocks. Both hardware and software tablewalks are provided for the TLBs.
Flexible Bus Interface
MPC755/745 microprocessors have a 64-bit data bus with 32-bit mode and a 32-bit address bus. Support is included for burst, split and pipelined transactions. The interface provides snooping for data cache coherency. Both microprocessors maintain MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices.
Superscalar Microprocessor
MPC755 and MPC745 microprocessors are superscalar, capable of issuing three instructions per clock cycle (two instructions + branch) into six independent execution units:
The ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for MPC755 and MPC745 systems.
Power Management
The MPC755 and MPC745 microprocessors feature a low-power 2.0-volt design with three power-saving user-programmable modes—doze, nap and sleep—which progressively reduce the power drawn by the processor.
These low-power microprocessors offer dynamic power management to selectively activate functional units as they are needed by the executing instructions. Both microprocessors also provide a thermal assist unit and instruction cache throttling for software-controllable thermal management.
Cache and MMU Support
The MPC755/745 microprocessors have separate 32-Kbyte, physically-addressed instruction and data caches. Both caches can be locked in part or whole to provide storage of critical data, key performance algorithms, or code loops for fast response time. The MPC755 microprocessor's dedicated L2 cache interface with on-chip L2 tags (up to 1MB) features support for direct-mapped SRAM mode, physically-mapped SRAM mode, a fast (typically 1/2 core speed) interface to memory, instruction-only or data-only modes, and parity checking on both L2 address and data.
MPC755/745 microprocessors contain separate memory management units (MMUs) for instructions and data, supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Both feature eight instruction block address translation (iBAT) and eight data block address translation (dBAT) registers. Access privileges and memory protection are controlled on block or page granularities. Large, 128-entry translation lookaside buffers (TLBs) provide efficient physical address translation and support for virtual-memory management on both page- and variable-sized blocks. Both hardware and software tablewalks are provided for the TLBs.
Flexible Bus Interface
MPC755/745 microprocessors have a 64-bit data bus with 32-bit mode and a 32-bit address bus. Support is included for burst, split and pipelined transactions. The interface provides snooping for data cache coherency. Both microprocessors maintain MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices.