High-Performance Six-Core DSP with Security


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Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram


  • Six StarCore® DSP SC3850 core subsystems each with:
    • SC3850 DSP core at up to 1 GHz
    • 512 KB unified L2 cache/M2 memory
    • 32 KB I-cache, 32 KB D-cache
    • Fully programmable 1056 KB M3 shared memory (SRAM)
  • MAPLE-B - highly flexible programmable Turbo and Viterbi decoder supports configurable decoding parameters. It can perform up to 200 Mbps of Turbo decoding (six iterations) or up to 115 Mbps of K = 9 (zero tail) Viterbi decoding
  • SEC (MSC8156E) optimized to process all the encryption/decryption algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, AES, DES, RC-4, SNOW-3G and Kasumi for 3G-LTE and 3GPP
  • Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz data rate
  • Chip-level arbitration and switching fabric, non-blocking, fully pipelined, low latency
  • High-speed interconnects:
    • Dual 4x/1x Serial RapidIO® at 1.25/2.5/3.125 Gbaud
    • PCI Express® 4x/1x
    • Two SGMII
  • Dual RISC QUICC Engine® supporting:
    • RGMII gigabit Ethernet ports
    • Serial peripheral interface (SPI)
  • TDM highway 1024 ch., 400 Mbps, divided into four ports of 256
  • DMA engine 16 bi-directional channels
  • Other peripheral interfaces:
    • UART
    • I²C
    • 32 GPIO
    • 16 timers
  • Technology
    • Process: 45 nm SOI
    • Voltage: 1-volt core, 2.5, 1.8/1.5-volt I/O
    • Package: FC-BPGA (29x29) 1 mm pitch, RoHS


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