100-250 MHz MPC603e Processor core
- 32-bit PCI interface operating at up to 66 MHz
- Memory controller offering SDRAM support up to 100 MHz operation
- General Purpose I/O and ROM Interface Support
- Two-channel DMA controller that supports chaining
- Messaging unit with I2O messaging support capability
- Industry-standard I2C interface
- Programmable interrupt controller with multiple timers and counters
Typical Applications
- Routers/Switches
- Multi-channel modems
- Network storage
- Image display systems
- Enterprise I/O processor
- Internet access device (IAD)
- Disk controller for RAID systems
- Copier/printer board control
Processor Core and On-Chip Peripheral Logic Features
- MPC603e processor core
- High-performance, superscalar processor core
- Floating-point unit (selectable), integer, load/store, system register
and branch processing unit
- 16K instruction cache, 16K data cache
- Lockable portion of L1 cache
- Dynamic power management
- Memory interface
- 100 MHz memory bus capability
- Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM
- High-bandwidth bus (32/64-bit data bus) to DRAM
- Supports one to eight banks of 4-, 16-, 64- or 128-Mbit DRAM
- Supports 1 Mbyte to 1 Gbyte DRAM memory
- Contiguous memory mapping
- 16 Mbytes of ROM space
- 8-bit, 32-bit, or 64-bit ROM
- Supports bus-width writes to flash
- Read-modify-write parity support (selectable)
- ECC support (selectable)
- SDRAM, DRAM buffer data-path
- Error injection/capture on data path
- LVTTL compatible
- PortX: 8-, 32- or 64-bit general-purpose I/O port uses ROM controller
interface with address strobe
- 32-bit PCI interface operating up to 66 MHz
- PCI 2.1 compatible
- PCI 5.0 V tolerant
- Support for PCI locked accesses to memory
- Support for accesses to all PCI address spaces
- Selectable big- or little-endian operation
- Store gathering of processor-to-PCI writes and PCI-to-memory writes
- Memory prefetching of PCI read accesses
- Parity support (selectable)
- Selectable hardware-enforced coherency
- PCI bus arbitration unit (5 request/grant pairs)
- PCI agent mode capability
- Address Translation Unit (ATU)
- Run time register access
- PCI configuration register access
- Two-channel integrated DMA controller
- Supports direct or chaining modes
- Scatter gather
- Interrupt on completed segment, chain, and error
- Local to local memory
- PCI to PCI memory
- PCI to local memory
- Local to PCI memory
- Message Unit
- (I2O) Intelligent Input/Output Message Controller
- Two door-bell registers
- Inbound and outbound messaging registers
- (I2C) Inter-Integrated Circuit Controller
- Full master/slave support
- Embedded programmable interrupt controller (EPIC)
- Five hardware interrupts (IRQs) or 16 serial interupts
- Four programmable timers
- Integrated PCI bus and SDRAM clock generation
- Programmable memory and PCI bus drivers
- Debug Features
- Watchpoint monitor
- Memory attribute and PCI attribute signals
- JTAG/COP Common On-board Processor for in-circuit hardware debugging
