4-Bit LVTTL-to-GTL Transceiver

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Block Diagram

GTL2014

GTL2014 Block Diagram

Features

Key Features

  • Operates as a 4-bit GTL-/GTL/GTL+ sampling receiver or as a LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
  • GTL input and output 3.6 V tolerant
  • Vref adjustable from 0.5 V to VCC/2
  • Partial power-down permitted
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101
  • Latch-up protection exceeds 500 mA per JESD78
  • Package offered: TSSOP14

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Documentation

Quick reference to our documentation types

8 documents

Compact List

Application Note (1)
Data Sheet (1)
Package Information (2)
Packing Information (1)
Selector Guide (1)
Supporting Information (1)
Training Presentation (1)

Design Files

Quick reference to our design files types.

2 design files

Engineering Services

2 engineering services

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