Design Files
2 design files
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Models
GLT2005 IBIS model
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Symbols and Footprints
GTL2005PW-TSSOP14-CAD Symbol and PCB Footprint – BXL File
Quad GTL/GTL+ to LVTTL/TTL Bidirectional Non-Latched Translator
GTL2005PW Receive alerts
- Not Recommended for New Designs
- This page contains information on a product that is not recommended for new designs.
GTL2005PW device is "End of Life", please use the replacement part GTL2014PW
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS outputs.
The GTL2005 Vref linearity degrades below 0.8 V (see Section 10.1). If the application allows, use the GTL2014, otherwise more closely review noise margins.
TSSOP8
Product Details
Block Diagram
Features
Key Features
- Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+ driver
- Quad bidirectional bus interface
- 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
- Live insertion/extraction permitted
- Latch-up protection exceeds 500 mA per JESD78
- ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V CDM per JESD22-CC101
- Package offered: TSSOP14
Documentation
Quick reference to our documentation types.
1-5 of 10 documents
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Application Note
AN10145 Bi-directional low voltage translators
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Application Note
AN10216
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User Guide
I2C-bus specification and user manual
Design Resources
Hardware
Engineering Services
To get further assistance directly from NXP, please see our Engineering Services.
2 engineering services
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Independent Design House (IDH)
Hardware Design Services
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Independent Design House (IDH)
Embedded Software Design
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