DSP56321T: 24-Bit Digital Signal Processor ARCHIVED

High-performance DSP56300 Core:

• 220/240 MMACS (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block- transfer interrupts; and triggering from interrupt lines and all peripherals
• Digital Phase Lock Loop (DPLL) allows change of low-power Divide Factor (DF) without loss of lock
• Hardware debugging support including On-Chip Emulation (OnCE^TM) module, Joint Test Action Group (JTAG) Test Access Port (TAP)

Enhanced Filter Coprocessor (EFCOP)-an on-chip 24 x 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core On-Chip Memories and Off-Chip Memory Expansion:

• 192 K x 24-bit on-chip RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

Program RAM Size	Instruction Cache Size	X Data RAM Size*	Y Data RAM Size*
32 K x 24-bit	0	80 K x 24-bit	80 K x 24-bit
31 K x 24-bit	1024 x 24-bit	80 K x 24-bit	80 K x 24-bit
40 K x 24-bit	0	76 K x 24-bit	76 K x 24-bit
39 K x 24-bit	1024 x 24-bit	76 K x 24-bit	76 K x 2 4-bit
48 K x 24-bit	0	72 K x 24-bit	72 K x 24-bit
47 K x 24-bit	1024 x 24-bit	72 K x 24-bit	72 K x 24-bit
64 K x 24-bit	0	64 K x 24-bit	64 K x 24-bit
63 K x 24-bit	1024 x 24-bit	64 K x 24-bit	64 K x 24-bit
72 K x 24-bit	0	60 K x 24-bit	60 K x 24-bit
71 K x 24-bit	1024 x 24-bit	60 K x 24-bit	60 K x 24-bit
80 K x 24-bit	0	56 K x 24-bit	56 K x 24-bit
79 K x 24-bit	1024 x 24-bit	56 K x 24-bit	56 K x 24-bit
96 K x 24-bit	0	48 K x 24-bit	48 K x 24-bit
95 K x 24-bit	1024 x 24-bit	48 K x 24-bit	48 K x 24-bit
112 K x 24-bit	0	40 K x 24-bit	40 K x 24-bit
111 K x 24-bit	1024 x 24-bit	40 K x 24-bit	40 K x 24-bit

* Includes 12 K x 24-bit shared memory (that is, memory shared by the core and the EFCOP).
• 192 x 24-bit bootstrap ROM

Off-chip memory expansion:

• Data memory expansion to two 256 K x 24-bit word memory spaces using the standard external address lines
• Program memory expansion to one 256 K x 24-bit word memory space using the standard external address lines
• External memory expansion port
• Chip Select Logic for glueless interface to SRAMs

On-Chip Peripherals:

• 3.3 V I/O interface Enhanced DSP56000-like 8-bit parallel Host Interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1), each with one receiver and three transmitters
• Serial Communications Interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable General-Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled

Reduced Power Dissipation:

• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (DC)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)

Packaging: 196-pin FC-PBGA