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The NXP analog product development boards provide an easy-to-use platform for evaluating NXP products. The boards support a range of analog, mixed-signal and power solutions. They incorporate monolithic integrated circuits and system-in-package devices that use proven high-volume technology. NXP products offer longer battery life, a smaller form factor, reduced component counts, lower cost and improved performance in powering state-of-the-art systems.
This page will guide you through the process of setting up and using the KITFS86SKTFRDMEM board.
The contents include:
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In addition to the kit contents, the following hardware is necessary or beneficial when working with this board:
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This evaluation board requires a Windows PC workstation. Meeting these minimum specifications should produce positive results when working with this evaluation board:
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Installing software is necessary to work with this evaluation board. All listed software is available on the evaluation board's information page at KITFS86SKTFRDMEM or from the provided link.
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The KITFS86SKTFRDMEM provides flexibility to play with all the features of the device and make measurements on the main part of the application. The KL25Z MCU freedom board plugged on the board, combined with the NXP GUI software allows access to the registers in read and write mode. All regulators are accessible through connectors. Nonuser signal, like DC-DC switcher node is mapped on test points. Digital signals (I²C, RSTB, and so on) are accessible through connectors. Pin WAKE1 has a switch to control (ignition) them. A VBAT switch is available to power on or off the device. The main purpose of this kit is to burn the OTP configuration. This kit can be operated in emulation mode or in OTP mode. In emulation mode, as long as the power is supplied, the board configuration stays valid, however the fail-safe configuration is lost if the device goes into deep fail-safe. The OTP mode uses the fused configuration. The device can be fused two times. In OTP mode, the device always starts with the fused configuration, except if the user wants to overwrite the OTP configuration using emulation mode. This board is able to fuse the OTP without any extra tools or board.
Note: Due to the socket, this kit is not optimized for performance measurement or current higher than 1.0 A.
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Figure 1. Identifies important components on the board and Table 1 provides additional details on these components.
Table 1. Evaluation board featured components location.
| Number | Description |
|---|---|
| 1 | LDO1 / LDO2 power supply |
| 2 | BUCK / BOOST power supply |
| 3 | VBAT Jack connector |
| 4 |
VBAT three position switch
|
| 5 | VBAT Phoenix connector |
| 6 | VPRE power supply |
| 7 | USB connectors (Open SDA for MCU flash; KL25Z for NXP GUI control) |
| 8 | Debug connectivity. Access to FS8600 signals |
| 9 | External regulator connectors (to VMONx) |
| 10 | VMONx configuration (Choice between monitoring a regulator or a fixed 0.8 V) |
| 11 | OTP and DBG switch |
| 12 | FCCU switch |
| 13 | VPRE compensation network settings (455 kHz or 2.22 MHz) |
| 14 | VDDI2C selection |
| 17 | KL25Z freedom board connectors |
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The device configuration can be changed twice. The programming steps are described in the NXP GUI for FS86 automotive family user manual available at NXP GUI for Automotive PMIC FamiliesNXP GUI for Automotive PMIC Families.
Figure 2 presents a typical hardware configuration incorporating the development board, power supply and Windows PC workstation.
To configure the hardware and workstation as illustrated in Figure 2, complete the following procedure:
Table 2. Hardware configuration.
| Switch | Configuration | |||
|---|---|---|---|---|
| Normal mode | Debug mode entry | OTP mode entry | ||
| Operation | watchdog 2s window | watchdog window fully open | OTP emulation / programming and Debug mode entry | |
SW1 (WAKE1) |
close (WAKE1 high) | |||
SW2 (VBAT) |
middle position (VBAT OFF) | |||
SW7 (DBG_OTP) |
1-4 open (DBG mode OFF) 2-3 open (OTP mode OFF) |
2-3 close (OTP mode ON) | ||
|
2-3 open (OTP mode OFF) 1-4 close (DBG = 4.5 V) |
||||
J6)SW2 in TOP positionTo configure the hardware and workstation as illustrated in Figure 3, complete the following procedure:
J6)At this step, if the product is in OTP mode entry configuration, all regulators are Off. The user can power up with an OTP configuration or configure the mirror registers before powering up. Power-up starts as soon as one of these three functions occurs:
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In addition to our FS86: Safety System Basis Chip For Domain Controller, Fit For ASIL B and D page, you may also want to visit:
Application pages: