Bootable CPU RTC with Two I2C Buses, 128 Byte SRAM and Alarm Function

PCF85053A

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Block Diagram

Bootable CPU RTC with Two I2C Buses, 128 Byte SRAM and Alarm Function

PCF85053A Block Diagram

Features

Operating Voltage

  • Supply voltage: 1.7 V to 3.6 V
  • Battery supply voltage: 1.55 V to 3.6 V

Communication Interface

  • Two independent I2C interfaces:
    • Primary I2C bus: read / write capability on RTC and SRAM registers
    • Second I2C bus: read / write capability on RTC and SRAM registers enabled by primary I2C
  • I2C device addresses:
    • RTC: 1101 111
    • SRAM: 1010 111
  • I2C clock features:
    • Max CLK frequency 400 kHz
    • Max CLK timeout 35 ms
  • I2C bus not active when switch over to battery

Real Time Clock Features

  • Real-time clock and calendar
  • Provides year, month, day, weekday, hours, minutes and seconds based on a 32.768 kHz quartz crystal
  • Support both binary mode and BCD mode
  • Support 24-hour and 12-hour mode
  • Support daylight saving mode
  • Oscillator fail flag
  • RTC clear flag
  • RTC fail flag
  • Alarm flag

Extra Features

  • Active low alert interrupt output
  • Register definition aligned to MC146818B (0 to 9 h)
  • Configurable oscillator circuit for a wide variety of quartzes: CL = 6 pF, CL = 7 pF, and CL = 12.5 pF
  • Operating temperature range -40 °C to 85 °C
  • Battery-backed 128 byte SRAM
  • SRAM clear to ‘0’ by RTC_CLR# pin
  • Frequency adjustment via programmable offset register

Part numbers include: PCF85053ATK.

Documentation

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2 documents

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Hardware

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