1 design file
Symbols and Footprints
PCA9847PW-TSSOP24-CAD Symbol and PCB Footprint – BXL File
The PCA9847 is an ultra-low voltage, octal bidirectional translating multiplexer controlled via the I²C-bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any single SCx/SDx channel can be selected, determined by the programmable control register. This feature allows multiple devices with the same I²C-bus address to reside on the same bus. The multiplexer device can also separate a heavily loaded I²C-bus into separate bus segments, eliminating the need for a bus buffer.
An active LOW reset input allows the PCA9847 to recover from a situation where one of the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine and deselects all the channels, as does the internal Power-On Reset (POR) function.
The pass gates of the multiplexers are constructed such that the VDD1 pin is used to limit the maximum high voltage which is passed by the PCA9847. This allows the use of different bus voltages on each channel, so that 0.8 V, 1.8 V, 2.5 V or 3.3 V parts can communicate without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 3.6 V tolerant.
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1 design file