Design Files
2 design files
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Models
DSP56321 IBIS Model File
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Models
DSP56321 BSDL File PBGA196 Mask K91M
This product has been discontinued. See DSP56321.
The NXP® DSP56321T, a member of the DSP56300 family of programmable Digital Signal Processors (DSPs), supports network applications with general filtering operations. The on-chip Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations to provide enhanced signal quality without affecting channel throughput or total number of channels supported, resulting in increased overall performance. Like the other family members, the DSP56321T uses a high-performance, single clock cycle per instruction engine, a barrel shifter, 24-bit addressing, instruction cache, and Direct Memory Access (DMA) controller. The DSP56321T offers 220/240 MMACS performance (440/480 MMACS using the EFCOP in filtering applications) using an internal 220/240 MHz clock, a 1.6 V core, and independent 3.3 V Input/Output (I/O).
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