Integrated Cellular Baseband Processor

Overview

The DSP56652 has been placed on "Not Recommended for New Designs" status. This is NOT an End-of-Life Notice.

The ROM-based DSP56652 is designed to support the rigorous demands of the cellular subscriber market. The high level of on-chip integration in the DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations.

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Features

RISC M·CORE MCU

32-bit load/store RISC architecture
Fixed 16-bit instruction length
16-entry 32-bit general-purpose register file
32-bit internal address and data buses
Efficient four-stage, fully interlocked execution pipeline
Single-cycle execution for most instructions, two cycles for branches and memory accesses
Special branch, byte, and bit manipulation instructions
Support for byte, half-word, and word memory accesses
Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file

High-performance DSP56600 core

1 x engine (e.g., 70 MHz = 70 MIPS)
Fully pipelined 16 x 16-bit parallel Multiplier-Accumulator (MAC)
Two 40-bit accumulators including extension bits
40-bit parallel barrel shifter
Highly parallel instruction set with unique DSP addressing modes
Position-independent code support
Nested hardware DO loops
Fast auto-return interrupts
On-chip support for software patching and enhancements
Realtime trace capability via external address bus

On-chip memories

4K x 32-bit MCU ROM
512 x 32-bit MCU RAM
48K x 24-bit DSP Program ROM
512 x 24-bit DSP Program RAM
20K x 16-bit DSP data ROM, split into 10K x 16-bit each of X and Y data ROM spaces
14K x 16-bit DSP data RAM, split into (7 + 1)K x 16-bit X data RAM and 6K x 16-bit Y data RAM spaces

On-chip peripherals

Fully programmable Phase-locked Loop (PLL) for DSP clock generation
External Interface Module (EIM) for glueless system integration
External 22-bit address and 16-bit data MCU buses
Thirty-two source MCU Interrupt Controller
Intelligent MCU/DSP Interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control
Serial audio codec port
Serial baseband codec port
Protocol timer frees the MCU from radio channel timing events
Queued Serial Peripheral Interface (SPI)
Keypad port capable of scanning up to an 8 x 8 matrix keypad
General-purpose MCU and DSP timers
Pulse width modulation (PWM) output
Universal Asynchronous Receiver/Transmitter (UART) with FIFO
IEEE 1149.1-compliant boundary scan JTAG Test Access Port (TAP)
Integrated DSP/M·CORE On-Chip Emulation (OnCE™) module
DSP Address Bus Visibility mode for system development
ISO 7816-compatible SmartCard port

Operating features

Comprehensive static and dynamic power management
M·CORE operating frequency: dc to 16.8 MHz at 1.8 V or dc to 40 MHz at 2.5 V
DSP operating frequency: dc to 58.8 MHz at 1.8 V or dc to 70 MHz at 2.5 V
Internal operating voltage range: 1.8-2.5 V with 3.3 V-tolerant I/O
Operating temperature: -40° to 85°C ambient
Package option: 15 x 15 mm, 196-lead PBGA

MoreLess

Features

RISC M·CORE MCU

32-bit load/store RISC architecture
Fixed 16-bit instruction length
16-entry 32-bit general-purpose register file
32-bit internal address and data buses
Efficient four-stage, fully interlocked execution pipeline
Single-cycle execution for most instructions, two cycles for branches and memory accesses
Special branch, byte, and bit manipulation instructions
Support for byte, half-word, and word memory accesses
Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file

High-performance DSP56600 core

1 x engine (e.g., 70 MHz = 70 MIPS)
Fully pipelined 16 x 16-bit parallel Multiplier-Accumulator (MAC)
Two 40-bit accumulators including extension bits
40-bit parallel barrel shifter
Highly parallel instruction set with unique DSP addressing modes
Position-independent code support
Nested hardware DO loops
Fast auto-return interrupts
On-chip support for software patching and enhancements
Realtime trace capability via external address bus

On-chip memories

4K x 32-bit MCU ROM
512 x 32-bit MCU RAM
48K x 24-bit DSP Program ROM
512 x 24-bit DSP Program RAM
20K x 16-bit DSP data ROM, split into 10K x 16-bit each of X and Y data ROM spaces
14K x 16-bit DSP data RAM, split into (7 + 1)K x 16-bit X data RAM and 6K x 16-bit Y data RAM spaces

On-chip peripherals

Fully programmable Phase-locked Loop (PLL) for DSP clock generation
External Interface Module (EIM) for glueless system integration
External 22-bit address and 16-bit data MCU buses
Thirty-two source MCU Interrupt Controller
Intelligent MCU/DSP Interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control
Serial audio codec port
Serial baseband codec port
Protocol timer frees the MCU from radio channel timing events
Queued Serial Peripheral Interface (SPI)
Keypad port capable of scanning up to an 8 x 8 matrix keypad
General-purpose MCU and DSP timers
Pulse width modulation (PWM) output
Universal Asynchronous Receiver/Transmitter (UART) with FIFO
IEEE 1149.1-compliant boundary scan JTAG Test Access Port (TAP)
Integrated DSP/M·CORE On-Chip Emulation (OnCE™) module
DSP Address Bus Visibility mode for system development
ISO 7816-compatible SmartCard port

Operating features

Comprehensive static and dynamic power management
M·CORE operating frequency: dc to 16.8 MHz at 1.8 V or dc to 40 MHz at 2.5 V
DSP operating frequency: dc to 58.8 MHz at 1.8 V or dc to 70 MHz at 2.5 V
Internal operating voltage range: 1.8-2.5 V with 3.3 V-tolerant I/O
Operating temperature: -40° to 85°C ambient
Package option: 15 x 15 mm, 196-lead PBGA

Data Sheets

Application Notes

DSP56652: Integrated Cellular Baseband Processor ARCHIVED

Overview

Features

Features