Technical content and expertise to help jump start your design and get you to production faster.
As of September 25, 2003, Tundra Semiconductor Corporation has acquired Our MPC106 and MPC107 PCI Bridge/Memory Controller product family. As a result of this acquisition, Tundra Semiconductor Corporation will assume all sales, support or development for these devices--now known as the Tsi106 and Tsi107. After November 24, 2003, product information and technical documentation will be solely provided on Tundra Semiconductor Corporation's website at www.tundra.com/Tsi106. If you have any questions regarding this acquisition, please contact sales@tundra.com.
The MPC106 PCI Bridge/Memory Controller provides a bridge between the Peripheral Component Interconnect (PCI) bus and Our MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 Power Architecture host processors. PCI support allows system designers to design systems quickly using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC106 integrates secondary cache control and a high-performance memory controller that supports DRAM, SDRAM, EDO DRAM, ROM and Flash ROM. The MPC106 uses an advanced, 3.3-volt CMOS process technology and is fully compatible with TTL devices.
Archived content is no longer updated and is made available for historical reference only.
The MPC106 supports a programmable interface to MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 microprocessors operating at bus frequencies up to 83.3 MHz. The MPC106 processor interface allows for a variety of system configurations by providing support for either a second processor or a secondary (L2) cache. The L2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache.
The MPC106 PCI interface is designed to connect the processor and memory buses to the PCI local bus without the need for "glue" logic. The MPC106 acts as a master on the PCI bus.
The memory interface controls processor and PCI interactions to main memory. It supports a variety of DRAM, SDRAM or EDO DRAM, and ROM or Flash ROM configurations.
The MPC106 provides hardware support for four levels of power reduction-nap, doze, sleep, and suspend. The MPC106 design is fully static, allowing internal logic states to be preserved during all power saving modes.
The MPC106 supports a programmable interface to MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 microprocessors operating at bus frequencies up to 83.3 MHz. The MPC106 processor interface allows for a variety of system configurations by providing support for either a second processor or a secondary (L2) cache. The L2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache.
The MPC106 PCI interface is designed to connect the processor and memory buses to the PCI local bus without the need for "glue" logic. The MPC106 acts as a master on the PCI bus.
The memory interface controls processor and PCI interactions to main memory. It supports a variety of DRAM, SDRAM or EDO DRAM, and ROM or Flash ROM configurations.
The MPC106 provides hardware support for four levels of power reduction-nap, doze, sleep, and suspend. The MPC106 design is fully static, allowing internal logic states to be preserved during all power saving modes.