MPC106: PCI Bridge/Memory Controller ARCHIVED

NXP^® MPC106 PCI Bridge/Memory Controller

Multiprocessor and L2 Cache Support

The MPC106 supports a programmable interface to MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 microprocessors operating at bus frequencies up to 83.3 MHz. The MPC106 processor interface allows for a variety of system configurations by providing support for either a second processor or a secondary (L2) cache. The L2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache.

PCI Bus Support

The MPC106 PCI interface is designed to connect the processor and memory buses to the PCI local bus without the need for "glue" logic. The MPC106 acts as a master on the PCI bus.

Integrated Memory Controller

The memory interface controls processor and PCI interactions to main memory. It supports a variety of DRAM, SDRAM or EDO DRAM, and ROM or Flash ROM configurations.

Power Management

The MPC106 provides hardware support for four levels of power reduction-nap, doze, sleep, and suspend. The MPC106 design is fully static, allowing internal logic states to be preserved during all power saving modes.

MPC106 Major Features

Processor Interface

• Processor frequency up to 350 MHz and processor bus frequency up to 83.3 MHz
• 64-bit data bus and 32-bit address bus
• Provides support for either an external L2 cache or a secondary processor
• Full memory coherency supported

Secondary cache control

• 256-Kbyte, 512-Kbyte, 1-Mbyte sizes
• Direct-mapped
• Provides support for either asynchronous SRAM, burst SRAM, or
• Supports external lookaside L2 cache controller

PCI Interface

• Compliant with PCI specification, revision 2.1
• Interface operates up to 33 MHz
• 3.3-volt/5.0-volt compatible
• Read and write buffers to improve PCI performance
• Concurrent transactions on processor and PCI busses supported

Memory Interface

• Supports page mode DRAM, SDRAM, or EDO DRAM
• High-bandwidth (64-bit) data bus
• Supports 1 to 8 banks built of x1, x4, x8, x9, x16 or x18 DRAM chips
• 1 Gbyte of RAM space, 16 Mbytes of ROM space
• Supports writing to Flash EPROMs
• Supports parity or error-correcting code (ECC)

IEEE 1149.1-compliant, JTAG boundary-scan interface

304-pin ball grid array (BGA) package

Extended Temperature Availability

NXP offers MPC106 controllers at industrial (-40 to +105 degrees Celsius Tj) temperature ranges. Thomson TCS offers NXP MPC106 controllers at industrial and military (-55 to +125 degrees Celsius) operating ranges. Chip Supply, Inc. offers NXP MPC106 controllers at industrial and military operating ranges as well as known-good die.