MPC857DSL: PowerQUICC^® Processor with CPM (1 SCC, 1 SMC), 10/100 Ethernet ARCHIVED

The following list summarizes the key MPC857DSL features:

• Embedded MPC8xx core
• Single-issue, 32-bit version of the core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
• The MPC857DSL provides enhanced ATM functionality over that of the MPC860SAR. The MPC857DSL adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
  • Multiple APC priority levels available to support a range of traffic pace requirements
  • Port-to-port switching capability without the need for RAM-based microcode
  • Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
  • Parameter RAM for both SPI and I²C can be relocated without RAM-based microcode
  • Supports full-duplex UTOPIA master (ATM side) operation using a "split" bus
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• UTOPIA port supports up to 4 PHY addresses
• Complete static design
• Memory controller (eight banks)
• General-purpose timers
• Fast Ethernet controller (FEC)
• System integration unit (SIU)
• Interrupts
• Communications processor module (CPM)
• Four baud rate generators
• One SCC (serial communication controller) for Ethernet (SCC1)
• One SMC (serial management channel) for UART (SMC1)
• One SPI (serial peripheral interface)
• One I²C (inter-integrated circuit) port
• Parallel interface port (PIP)
• One PCMCIA socket (Port B)
• Low power support
• Debug interface
• 3.3 V core, 3.3 V I/O
• 357-pin ball grid array (BGA) package

The 857DSL is rated as a commercial quality product. Please contact your NXP^® Field Sales Representative or the NXP factory for more details.