MPC857T: PowerQUICC^® Processor with CPM (1 SCC, 2 SMC), 10/100 Ethernet ARCHIVED

The following list summarizes the key MPC857T features:

• Embedded MPC8xx core
• Single-issue, 32-bit version of the core (compatible with the Power Architecture definition) with 32, 32-bit general-purpose registers (GPRs)
• The MPC857T provides enhanced ATM functionality over that of the MPC860SAR. The MPC857T adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
  • Multiple APC priority levels available to support a range of traffic pace requirements
  • Port-to-port switching capability without the need for RAM-based microcode
  • Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
  • Parameter RAM for both SPI and I²C can be relocated without RAM-based microcode
  • Supports full-duplex UTOPIA master (ATM side) operation using a "split" bus
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Complete static design
• Memory controller (eight banks)
• General-purpose timers
• Fast Ethernet controller (FEC)
• System integration unit (SIU)
• Interrupts
• Communications processor module (CPM)
• Four baud rate generators
• One SCC (serial communication controller)
• Two SMCs (serial management channels)
• One SPI (serial peripheral interface)
• One I²C (inter-integrated circuit) port
• Time-slot assigner (TSA)
• Parallel interface port (PIP)
• PCMCIA interface
• Low power support
• Debug interface
• 3.3 V operation
• 357-pin ball grid array (BGA) package