MM912_634: Integrated HCS12 Based Relay Driver Microcontrollers (MCUs) with LIN

Overview

The MM912G634 (48 kB) and MM912H634 (64 kB) are integrated single package solutions that integrate an HCS12 MCU with a SMARTMOS^® analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application-specific functions, including a LIN transceiver.

Your customer benefits include:

Integrated MCU and analog features in the same package solution
A full LIN solution
Easy control of high-current motors using relays and current sense features
Reduced space, resulting in enhanced reliability
Full protection for output stages
Economical multifunction solution with few components
Low-power mode flexibility
Reverse-battery-protected voltage sense

View internal diagram

Features

CPU Core

16-Bit S12 CPU, 64/48/32 kByte Program Flash
4/2/0 kByte Data Flash
6/2/2 kBytes of RAM
Background debug (BDM) & debug module (DBG)
16-Bit, 4 Channel - Timer Module (TIM16B4C)
Die to Die bus interface for transparent memory mapping

Standard I/O

6 or 10 digital MCU GPIOs shared with SPI
10-Bit, 15 Channel - Analog to Digital Converter (ADC)
8-Bit, 2 Channel - Pulse width modulation module (PWM)

Application Specific Functions

On-chip oscillator & two independent watchdogs
LIN 2.1 Physical Layer Interface with integrated SCI
Six high voltage / Wake-up inputs (L5…0)
Three low voltage GPIOs (PB2…0)
Low power modes with cyclic sense & forced wake-up
Two protected low side outputs to drive inductive loads
Two protected high side outputs
Hall sensor supply & integrated voltage regulator(s)
Reverse battery protected voltage sense module
Chip temperature sensor
Current sense module with selectable gain

Product Longevity

The MM912F634 is included in NXP^®.s product longevity program, with assured supply for a minimum of 15 years after launch

Features

CPU Core

16-Bit S12 CPU, 64/48/32 kByte Program Flash
4/2/0 kByte Data Flash
6/2/2 kBytes of RAM
Background debug (BDM) & debug module (DBG)
16-Bit, 4 Channel - Timer Module (TIM16B4C)
Die to Die bus interface for transparent memory mapping

Standard I/O

6 or 10 digital MCU GPIOs shared with SPI
10-Bit, 15 Channel - Analog to Digital Converter (ADC)
8-Bit, 2 Channel - Pulse width modulation module (PWM)

Application Specific Functions

On-chip oscillator & two independent watchdogs
LIN 2.1 Physical Layer Interface with integrated SCI
Six high voltage / Wake-up inputs (L5…0)
Three low voltage GPIOs (PB2…0)
Low power modes with cyclic sense & forced wake-up
Two protected low side outputs to drive inductive loads
Two protected high side outputs
Hall sensor supply & integrated voltage regulator(s)
Reverse battery protected voltage sense module
Chip temperature sensor
Current sense module with selectable gain

Product Longevity

The MM912F634 is included in NXP^®.s product longevity program, with assured supply for a minimum of 15 years after launch

Application Notes

HCS12 Block Diagram

HCS12 Block Diagram

NXP^® MM912_634 Product Image

NXP<sup>®</sup> MM912_634 Product Image

HCS12 Block Diagram
NXP^® MM912_634 Product Image

HCS12 Block Diagram

HCS12 Block Diagram

NXP^® MM912_634 Product Image

NXP<sup>®</sup> MM912_634 Product Image

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Target Applications

Communication Infrastructure

Broadband Modem and Residential Gateway

Technologies

Electric Pumps