Software Defined Radio Processor for V2X Communication

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Block Diagram

Software Defined Radio Processor for V2X Communication Block Diagram

Software Defined Radio Processor for V2X Communication Block Diagram

Features

  • Compliant with IEEE 802.11p and IEEE 1609.4
  • Compliant with ETSI EN 302 663
  • Compliant with ARIB T55 and ARIB T75 standards
  • Dual channel handling for diversity and concurrent control and service channel reception
  • Dual channel handling for cyclic transmit diversity transmission
  • Digital baseband processing, including In-phase Quadrature Compensation (IQC), Automatic Gain Control (AGC) control, decimation
  • DSP processing for demodulation and improvement algorithms
  • Outer receiver HWA for channel decoding and encoding
  • Arm processor domain for control Software (SW), interfacing and ITS MAC/LLC handling
  • Configurable booting from external serial flash or through the host (USB, SPI)
  • USB 2.0 high-speed peripheral interface
  • Qualified in accordance with AEC-Q100 Qualified
  • Synchronous Dynamic Random Access Memory (SDRAM) interface is not used for ITS applications
  • Serial communication ports, including Inter-Integrated Circuit bus (I2C-bus), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART)
  • Hardware timers and pulse width modulation blocks
  • Optional Elliptic Curve Digital Signature Algorithm (ECDSA) accelerator for authentication verification of messages

Design Resources

Documentation

Quick reference to our documentation types.

1 documents

Design Files

Hardware

3 hardware offerings

  • Complementary Silicon or Component

    V2X Radio Module

  • Complementary Silicon or Component

    V2X On Board Unit

  • Complementary Silicon or Component

    V2X Roadside Unit

Software

Engineering Services

1 engineering service

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Training

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