Design Files
Receive the full breakdown. See the product footprint and more in the eCad file.
High-Performance DisplayPort Gen2 2-1 Multiplexer
CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP® proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP212 is on motherboards where one of two GPU DisplayPort sources needs to be selected to connect to a DisplayPort sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the bidirectional nature of the signal paths, CBTL06DP212 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors.
sot918-1_3d
Product Details
Features
Key Features
- High-bandwidth: 5 GHz at -3 dB
- Low crosstalk: -35 dB at 3 GHz
- Low off-state isolation: -30 dB at 3 GHz
- Low return loss: -8 dB at 3 GHz
- Very low intra-pair skew (5 ps typical)
- Very low inter-pair skew (< 80 ps)
- Switch/multiplexer position select CMOS input
- DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
- Supports HDMI/DVI incorrect dongle connection
- Single 3.3 V power supply
- Operation current of 2 mA typical
- ESD 8 kV HBM, 1 kV CDM
- ESD 2 kV HBM, 500 V CDM for control pins
- Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package
1 : 2 Switching or 2 : 1 Multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) Signals
- 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort main link signals
- 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
- 1 channel with 2 : 1 multiplexing/switching for HPD signal
Low Insertion Loss
- -0.5 dB at 100 MHz
- -3 dB at 5 GHz
Buy/Parametrics
|
|
|
|
|
|
|
|---|---|---|---|---|---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Documentation
Quick reference to our documentation types.
3 documents
-
Package Information
plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm
Design Resources
Engineering Services
To get further assistance directly from NXP, please see our Engineering Services.
2 engineering services
-
Independent Design House (IDH)
Hardware Design Services
-
Independent Design House (IDH)
Embedded Software Design
To find additional partner offerings that support this product, visit our Partner Marketplace.