20 Gbps Per Lane, 4-Lane DisplayPort Linear Redriver

  • Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

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Block Diagram

PTN3816 Block Diagram

PTN3816 Block Diagram


Key Features

  • Implements DisplayPort linear redriver that can operate for various link rates -
  • 1.62 Gbps (RBR), 2.7 Gbps (HBR), 5.4 Gbps (HBR2), 8.1 Gbps (HBR3), 10, 13.5 and 20 Gbps
  • Supports configurable number of lanes: 1, 2 and 4
  • DP AUX monitoring for link configuration and power management
  • Implements Hot Plug Detect (HPD) for deep power saving
  • GPIO configurable output swing linearity control and Rx equalizer gain setting eliminates need for I2C register configuration
  • High-Speed redriver path supports DP++ mode that targets DP to HDMI interface use
  • Supports maximum voltage limit (Vvoltage_jump) to align to the latest system platform capabilities
  • Integrated termination resistors provide impedance matching on transmit and receive sides
  • Good linearity over the frequency band and voltage dynamic range
  • Excellent Differential return loss performance
  • Pin-out minimizes PCB crosstalk effects
  • Low active current consumption for output linearity control setting of 950 mVppd
    • 1-lane DP: 62 mA (typ)
    • 2-lane DP: 125 mA (typ)
    • 4-lane DP: 250 mA (typ)
  • Power–saving state:
  • DisplayPort sleep D3 mode: 3.2 mA (typ)
  • 10 μA (typ) when in deep power-saving state (when HPD is LOW)
  • Power Supply 1.7 V to 1.9 V
  • Small high performance HWFLGA36 package
    • 2.1 mm x 6.0 mm x 0.6 mm with 0.4 mm pitch
  • ESD HBM 1.5 kV CDM 1 kV
  • Operating temperature range -20 °C to +85 °C

Part numbers include: PTN3816EW.


Quick reference to our documentation types.

3 documents

Design Resources


1 hardware offering


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