Four-Channel Level Translating I²C-Bus/SMBus Repeater

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Block Diagram

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PCA9519 Block Diagram

PCA9519 Block Diagram

Block diagram: PCA9519BS, PCA9519PW

Block diagram: PCA9519BS, PCA9519PW


Key Features

  • 4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
  • Voltage level translation from port A (1 V to VCC(B) - 1.5 V) to port B (3.0 V to 5.5 V)
  • Requires no external pull-up resistors on lower voltage port A
  • Active HIGH repeater enable input
  • Open-drain inputs/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • Operating supply voltage range of 1.0 V to VCC(B) - 1.5 V on port A, 3.0 V to 5.5 V on port B
  • 5 V tolerant B-side SCL and SDA and enable pins
  • 50 ns glitch filter on B-side input
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: TSSOP20, HVQFN24
  • Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater

Part numbers include: PCA9519BS, PCA9519PW.


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