Level Translating I²C-Bus Repeater

Product Details

Select a section:

Block Diagram

Choose a diagram:

PCA9517 Block Diagram

PCA9517 Block Diagram

Block diagram: PCA9517D, PCA9517DP

Features

  • 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device
  • Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
  • Footprint and functional replacement for PCA9515/15A
  • I²C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard mode and Fast mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • A-side operating supply voltage range of 0.9 V to 5.5 V
  • B-side operating supply voltage range of 2.7 V to 5.5 V
  • 5 V tolerant I²C-bus and enable pins
  • 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater).
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 13 documents

Show All

Design Files

2 design files

Hardware

1 hardware offering

Engineering Services

2 engineering services

To find a complete list of our partners that support this product, please see our Partner Marketplace.

Support

What do you need help with?