Two-Channel I2C-Bus Switch with Interrupt Logic and Reset


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Block Diagram

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PCA9543A_43B Block Diagram

PCA9543A_43B Block Diagram

PCA9543AD, PCA9543APW, PCA9543BPW, PCA9543CPW Block Diagram


Key Features

  • 1-of-2 bidirectional translating switches
  • I2C-bus interface logic; compatible with SMBus standards
  • 2 active LOW interrupt inputs
  • Active LOW interrupt output
  • Active LOW reset input
  • 2 address pins allowing up to 4 devices on the I2C-bus
  • Alternate address versions A and B allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts
  • Channel selection via I2C-bus, in any combination
  • Power-up with all switch channels deselected
  • Low Ron switches
  • Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
  • No glitch on power-up
  • Supports hot insertion
  • Low standby current
  • Operating power supply voltage range of 2.3 V to 5.5 V
  • 5 V tolerant inputs
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO14, TSSOP14

Part numbers include: PCA9543AD, PCA9543APW.


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