Central Processing Unit (CPU32)
32 Bit Archirecture
Virtual Memory Implementation
Table Lookup and Interpolate Instruction
Improved Exception Handling for Controller Applications
High Level Language Support
Background Debugging Mode
Fully Static Operation
System Integration Module
External Bus Support
Programmable Chip Select Outputs
System Protection Logic
Watchdog Timer, Clock Monitor and Bus Monitor
Two 8 bit Dual Function Input/Output Ports
One 7 bit Dual Function Output Port
Phase-Locked Loop (PLL) Clock System
Time Processing Unit (TPU)
Dedicated Micro-Engine Operating Independently of CPU32
16 Independent Programmable Channels and Pins
Each Channel has an /Event Register Consisting of a 16 bit Capture Register, a 16 Bit
Compare Register and a 16 Bit Comparator
Any Channel can Perform Any Time Function
Each Channel has Six or Eight 16 Bit Parameter Registers
Each Timer FunctionMay Be Assigned to More Than One Channel
Two Timer Counter Registers with Programmable Prescalers
Each Channel Can Be Synchronized to Either or Both Counters
Selectable Channel Priority Levels
Configurable Timer Module Version 4 (CTM4)
Two 16 bit modulus counters (MCSM)
16 Bit Free-Running Counter (FCSM)
4 Double-action capture/compare channels, with PWM mode (DASM)
4 Dedicated PWM channels, each having its own 16 bit modulus counter (PWMSM)
Two Serial I/O Subsystems (QSM)
Enhanced serial communication interface (SCI)
Modulus baud rate generator
Parity detection
Queued serial peripheral interface (QSPI)
80 byte static RAM to perform queued operations
Up to 16 automatic transfers
Continuous cycling, 8 to 16 bits per transfer, LSB or MSB first
Dual function I/O pins
10 Bit Queued Analog-to-Digital Converter (QADC)
16 Channels internally; up to 41 directly accessible channels with external multiplexing
Six automatic channel selection and conversion modes
Two channel scan queues of veriable length, each with a variable number of sub-queues
40 Result registers and three result alignment formats
Programmable input sample time
Direct control of multiplexers
CAN 2.0B Controller Modules (TouCAN)
Full implementation of CAN protocol specification, version 2.0 A and B
16 receive/transmit message buffers of 0 to 8 bytes data length
Global mask register for message buffers 0 to 13
Independent mask registers for message buffers 14 and 15
Programmable transmit first scheme: lowest ID or lowest buffer number
16 bit free-running timer for message time-stamping
Low power sleep mode with programmable wake-up on bus activity
Masked ROM Module (MRM)
8 Kbyte array accessible as bytes or words
User selestable default base address
User selestable bootstrap ROM function
User selestable ROM verification code
3.5 Kbyte TPU Emulation RAM (TPURAM)
External VSTBY pin for separate standby supply
May be used as normal RAM or TPU emulation RAM
4 Kbytes of Static RAM
No Standby Supply
