PTN3460/PTN3460I - Commercial and Industrial E(DP) to LVDS Bridge IC

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Product Details

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Features

Device

  • Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility in firmware updates
  • LVDS panel power-up (/down) sequencing control
  • Firmware controlled panel power-up (/down) sequence timing parameters
  • No external timing reference needed
  • EDID ROM emulation to support panels with no EDID ROM. Emulation ON/OFF is set via configuration pin CFG4
    • Supports EDID structure v1.3
    • On-chip EDID emulation up to seven different EDID data structures
    • eDP complying PWM signal generation or PWM signal pass through from eDP source

DisplayPort Receiver

  • Compliant to DP v1.2a and v1.1a
  • Compliant to eDP v1.2 and v1.1
  • Supports Main Link operation with one or two lanes (select through configuration pin CFG3)
  • Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)
  • Supports 1 Mbit/s AUX channel
    • Supports Native AUX and I2C-over-AUX transactions
  • Supports down spreading to minimize EMI
  • Integrated 50 Ω termination resistors provide impedance matching on both Main Link lanes and AUX channel
  • High performance Auto Receive Equalization enabling optimal channel compensation, device placement flexibility and power saving at CPU/GPU
  • Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and Alternate Framing
  • Supports Full Link training
  • Supports DisplayPort symbol error rate measurements
  • Supports PCB routing flexibility by programming for:
    • AUX P/N swapping
    • DP Main Link P/N swapping

LVDS Transmitter

  • Compatible with ANSI/TIA/EIA-644-A-2001 standard
  • Supports RGB data packing as per JEIDA and VESA data formats
  • Supports pixel clock frequency from 6 MHz to 112 MHz
  • Supports single LVDS bus operation up to 112 mega pixels per second
  • Supports dual LVDS bus operation up to 224 mega pixels per second
  • Supports color depth options: 18 bpp, 24 bpp
  • Programmable center spreading of pixel clock frequency to minimize EMI
  • Supports 1920 x 1200 at 60 Hz resolution in dual LVDS bus mode
  • Programmable LVDS signal swing to pre-compensate for channel attenuation or allow for power saving
  • Supports PCB routing flexibility by programming for:
    • LVDS bus swapping
    • Channel swapping
    • Differential signal pair swapping
  • Supports Data Enable polarity programming
  • DDC control for EDID ROM access; I2C-bus interface up to 400 kbit/s

Control and System

  • Device programmability
    • Multi-level configuration pins enabling wider choice
    • I2C-bus target interface supporting Standard-mode (100 kbit/s) and Fast-mode (400 kbit/s)
  • Power management
    • Low-power state: DP AUX command-based Low-power mode (SET POWER)
    • Deep power-saving state via a dedicated pin

General

  • Power supply: with on-chip regulator
    • 3.3 V ± 10 % (integrated regulator switched on)
    • 3.3 V ± 10 %, 1.8 V ± 5 % (integrated regulator switched off)
  • ESD: 8 kV HBM, 1 kV CDM
  • Operating temperature range: -40 °C to +85 °C
  • HVQFN56 package 7 mm x 7 mm, 0.4 mm pitch; exposed center pad for thermal relief and electrical ground

PTN3460I Additional Features

  • Configurable CFG3 for to DP one or two lanes selection
  • Configurable CFG4 for EDID ROM emulation ON/OFF selection
  • Industrial temperature range -40 °C to 85 °C.

Product Longevity Program

  • This product is included in the NXP Product Longevity program ensuring a stable supply of products for your embedded designs. The PTN3460IBS/F2 is included in the 15-year program.

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