High-Speed CAN Core System Basis Chip


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Block Diagram

UJA1076ATW Block Diagram

UJA1076ATW Block Diagram



  • Designed for automotive applications according to ISO 11898-2/5
  • ±8 kV ESD protection Human Body Model (HBM) on the CAN/LIN bus pins and the wake-up pins
  • ±6 kV ESD protection IEC 61000-4-2 on the CAN/LIN bus pins and the wake-up pins
  • ±58 V short-circuit proof CAN/LIN bus pins
  • Battery and CAN/LIN bus pins are protected against transients in accordance with ISO 7637-3

Low-drop voltage regulators (LDOs)

  • V1 voltage regulator 5 V or 3.3 V with 250 mA output current capability
  • V1 can be combined with an external PNP transistor for better heat distribution over the PCB
  • V2 dedicated voltage regulator for CAN transceiver 5 V with 100 mA output current capability.

CAN transceiver

  • ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
  • SPLIT output pin for stabilizing the recessive bus level

System control features

  • Wake-up via CAN, LIN or two local wake-up pins with wake-up source detection
  • Programmable watchdog with independent clock source
  • 16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis
  • Global enable output for controlling safety-critical hardware
  • Limp home output (LIMP)


Quick reference to our documentation types.

2 documents

Design Resources

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