Third Generation High-Performance DisplayPort Multiplexer

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Block Diagram

CBTL06DP213

CBTL06DP213 Block Diagram

Features

General Features

  • 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.3 - 8.1 Gbit/s) signals
  • 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort main link signals
  • 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
  • 1 channel with 2 : 1 multiplexing/switching for HPD signal
  • High-bandwidth analog pass-gate technology
  • Ron on DP high-speed channels: 14 Ω
  • Low crosstalk: -35 dB at 2.7 GHz
  • Low off-state isolation: -30 dB at 2.7 GHz, -25 dB at 4 GHz
  • Very low intra-pair skew (5 ps typical)
  • Very low inter-pair skew (< 80 ps)
  • Switch/multiplexer position select CMOS input
  • DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
  • Supports HDMI/DVI incorrect dongle connection
  • Single 3.3 V power supply
  • Operation current of 2 mA typical,
  • ESD 2 kV HBM, 500 V CDM
  • Available in 5 mm x 5 mm, 0.5 mm ball pitch TFBGA48 package

Low Insertion Loss

  • - 0.9 dB at 100 MHz
  • - 1.3 dB at 2.7 GHz
  • - 1.7 dB at 4 GHz
  • - 3 dB at 11.1 GHz

Low Return Loss

  • - 20.3 dB at 100 MHz
  • - 16.7 dB at 1.35 GHz
  • - 12.9 dB at 2.7 GHz
  • - 12 dB at 4 GHz

Part numbers include: CBTL06DP213EE.

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Documentation

Quick reference to our documentation types.

3 documents

Design Files

Engineering Services

2 engineering services

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