LIN 2.1 / SAEJ2602-2, LIN Physical Layer

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Block Diagram

MC33662_BD

NXP<sup>&#174;</sup> MC33662 Internal Block Diagram

Features

  • Operational from a VSUP of 7.0 to 18 V DC, functional up to 27 V DC, and handles 40 V during Load Dump
  • Compatible with LIN Protocol Specification 1.3, 2.0, 2.1, and SAEJ2602-2
  • Active bus wave shaping, offering excellent radiated emission performance
  • Sustains up to 15.0 kV minimum ESD IEC61000-4-2 on the LIN Bus, 20 kV on the WAKE pin, and 25 kV on the VSUP pin
  • Very high immunity against electromagnetic interference
  • Low standby current in Sleep mode
  • Over-temperature protection
  • Local and remote Wake-up capability reported by the RXD pin
  • Fast baud rate selection reported by RXD pin
  • 5.0 V and 3.3 V compatible digital inputs without any required external components

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