LIN 2.2A/SAE J2602 Transceiver with TXD Dominant Timeout

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Block Diagram

LIN 2.2A/SAE J2602 Transceiver with TXD Dominant Timeout

TJA1029 Block Diagram



  • Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602
  • Baud rate up to 20 kBd
  • Very low ElectroMagnetic Emissions (EME)
  • Very low current consumption in Sleep mode with remote LIN wake-up
  • Input levels compatible with 3.3 V and 5 V devices
  • Integrated termination resistor for LIN follower applications
  • Passive behavior in unpowered state
  • Operational during cranking pulse: full operation from 5 V upwards
  • Undervoltage detection
  • K-line compatible
  • Available in SO8 and HVSON8 packages
  • Leadless HVSON8 package (3.0 mm x 3.0 mm) with improved Automated Optical Inspection (AOI) capability
  • Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant)
  • Pin-compatible subset of the TJA1020, TJA1021 and TJA1022
  • Pin-compatible with the TJA1027


  • Very high ElectroMagnetic Immunity (EMI)
  • Very high ESD robustness: ±8 kV according to IEC 61000-4-2 for pins LIN and VBAT
  • Bus terminal and battery pin protected against transients in the automotive environment (ISO 7637)
  • Bus terminal short-circuit proof to battery and ground
  • Thermally protected
  • Initial TXD dominant check when switching to Normal mode
  • TXD dominant time-out function


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1 hardware offering

  • N4 - Network Controller

    N4 - Network Controller


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