I²C-Bus Repeater


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Block Diagram

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PCA9515A Block Diagram

PCA9515A Block Diagram

Block diagram: PCA9515AD, PCA9515ADP


  • 2-channel, bidirectional buffer
  • I²C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • Operating supply voltage range of 2.3 V to 3.6 V
  • 5.5 V tolerant I²C-bus and enable pins
  • 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater)
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8, TSSOP8 (MSOP8), HWSON8


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Design Resources

Design Files

4 design files

  • Models

    PCA9515 IBIS model

  • Models

    PCA9515 IBIS model

  • Symbols and Footprints

    PCA9515AD-SO8-CAD Symbol and PCB Footprint – BXL File

  • Symbols and Footprints

    PCA9515ADP-TSSOP8-CAD Symbol and PCB Footprint – BXL File


2 hardware offerings

Engineering Services

2 engineering services

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