Level-Shifting Hot Swappable I²C-Bus and SMBus Bus Buffer

PCA9512A_PCA9512B

Product Details

Select a section:

Block Diagram

Choose a diagram:

PCA9512A-PCA9512B Block Diagram

PCA9512A-PCA9512B Block Diagram

Block diagram: PCA9512AD, PCA9512ADP

Block diagram: PCA9512AD, PCA9512ADP

Features

System Features

  • Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
  • Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards
  • Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ΔV/Δt rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same
  • 5 V to 3.3 V level translation with optimum noise margin
  • High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V
  • 1 V precharge on all SDAn and SCLn pins
  • Supports clock stretching and multiple controller arbitration and synchronization
  • Operating power supply voltage range: 2.7 V to 5.5 V
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8, TSSOP8 (MSOP8)

Documentation

Quick reference to our documentation types.

1-5 of 14 documents

Show All

Design Resources

Design Files

1 design file

Hardware

1 hardware offering

Engineering Services

2 engineering services

To find a complete list of our partners that support this product, please see our Partner Marketplace.

Support

What do you need help with?