Dual Universal Asynchronous Receiver/Transmitter (DUART)


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Product Details

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  • Member of IMPACT family: 3.3 V to 5.0 V , -40 Cel to +85 Cel and 80xx or 68k bus interface (I/M modes) for all devices.
  • Bit-by-bit real time transmission error check for high data integrity systems.
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 256 character FIFOs for each receiver and transmitter
  • Powers up to 9600 baud, 1 stop bit, no parity, 1 stop bit, interrupt disabled, all I/O set to input.
  • Pin programming to 68K or 80xxx bus interface
  • Three character recognition system per channel, used as:
    • General purpose character recognition
    • Xon/Xoff character recognition
    • Address recognition Wake up (multi-drop or '9 bit') mode
    • System provides 4 levels of automation on a recognition event
  • Programmable data format
    • 5 to 8 data bits plus parity and 9 bit mode
    • Odd, even, no parity or force parity
    • 9/16,1, 1.5 or 2 stop bits
  • 16-bit programmable Counter/Timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 27 fixed rates: 50 to 2.0 Meg baud (includes MIDI® rate)
    • Other baud rates via external clocks and C/T
    • Programmable user-defined rates derived from a programmable Counter/timer
    • External 1X or 16X clock
  • Parity, framing, and overrun error detection
  • Line break detection and generation; false start bit detection
  • Programmable channel mode
    • Normal (full-duplex)
    • Automatic echo
    • Local loop back
    • Remote loop back
    • Multi-drop mode (also called 'wake-up' or '9-bit')
  • Multi-function 8 bit I/O input port per channel loosely assigned to each channel.
    • Can serve as clock or control inputs
    • Change of state detection on eight inputs
    • Inputs have typically >100 M Ω pull-up resistors
    • Modem and DMA interface
  • Versatile arbitrating interrupt system
    • Interrupt system totally supports 'single query' polling
    • Output port can be configured to provide a total of up to six separate interrupt type outputs that may be wire-ORed (switched to open drain).
    • Each FIFO can be independently programmed for any of 256 interrupt levels
    • Watch dog timer for each receiver
  • Maximum data transfer rates: 1X - 3 Mb/sec, 16X - 2 Mb/sec
  • Automatic wake-up mode for multi-drop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • On-chip crystal oscillator
  • Power down mode at less than 10 ua
  • Receiver time-out mode
  • Single +3.3V or +5V power supply


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  • Symbols and Footprints

    SC28L202A1DGG-TSSOP56-CAD Symbol and PCB Footprint – BXL File

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