DSP56366: 24-bit Symphony^® DSP ARCHIVED

Multimode, multichannel decoder software functionality

Dolby and/or DTS license required.

• Dolby Digital
• MPEG^®2 5.1
• PCM
• DTS

Digital audio post-processing capabilities

• Bass managment
• Volume management
• Delay management
• ProLogic
• Graphic EQ
• Speaker Comp
• Treble/base loudness

Digital Signal Processing Core 

• 120 Million Instructions Per Second (MIPS) with a 120 MHz clock at 3.3 V.
• Object Code Compatible with the DSP56000 core with highly parallel instruction set
• Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support
• Program Control with position independent code support and instruction cache support
• Six-channel DMA controller
• PLL based clocking with a wide range of frequency multiplications (1 to 4096), predicider factors (1 to 16) and power saving clock divider (2^I: i=0 to 7). Reduces clock noise
• Internal address tracing support and OnCE^TM for Hardware/Software debugging
• JTAG port
• Very low-power CMOS design, fully static design with operating frequencies down to DC
• STOP and WAIT low-power standby modes

• 5 K - 7 K x 24 Bit Y-Data RAM and 8 K x 24 Bit Y-Data ROM
• 8 K - 13 K x 24 Bit X-Data RAM and 32 K x 24 Bit X-Data ROM
• 40 K x 24 Bit Program ROM
• 2 K -10 K x 24 Bit Program RAM and 192 x 24 Bit Bootstrap ROM. 1 K of Program RAM may be used as Instruction Cache or for Program ROM patching
• Various memory switches available

Off-chip memory expansion

• External Memory Expansion Port
• Off-chip expansion up to two 16 M x 24-bit word of Data memory
• Off-chip expansion up to 16 M x 24-bit word of Program memory
• Simultaneous glueless interface to SRAM and DRAM

• Enhanced Serial Audio Interface (ESAI_0): up to 4 receivers and up to 6 transmitters, leader or follower. I²S, Sony, AC97, network, and other programmable protocols.
• Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, leader or follower. I²S, Sony AC97, network, and other programmable protocols. The ESAI_1 shares four of the data pins with ESAI_0, and ESAI_1 does NOT support HCKR and HCKT (high speed clocks)
• Serial Host Interface (SHI): SPI and I²C protocols, 10-word receive FIFO, support for 8, 16, and 24-bit words.
• Byte-wide parallel Host Interface (HDI08) with DMA support
• Triple Timer module
• Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340, and AES/EBU digital audio formats
• Pins of unused peripherals (except SHI) may be programmed as GPIO lines