Design Files
2 design files
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Models
DSI Cycle-Accurate Model, Production Quality Tested
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Models
MSC8102 IBIS Model File
This product has been discontinued. See MSC8122.
The MSC8102 is a highly integrated system-on-a-chip that combines four StarCore® SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), and a multi-channel DMA controller. The four extended cores can deliver a total 4000/4400 DSP MMACS performance at 250/275 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8102 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8102 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.
The MSC8102 device is designed to provide an optimal solution for 3G wireless base stations, to help eliminate many of the costly and power hungry ASICs and FPGAs required in today's systems for both symbol rate and for chip rate assist. In addition, the MSC8102 device allows customers to add next-generation features that efficiently use available frequencies and higher bit rates in 3G systems.
Efficient application software development is key in Our strategy to expedite customers' time to market. Since the MSC8102 is based on the same extended core as the MSC8101 device, developers can take advantage of currently available development tools and real-time operating systems (RTOS) from Metrowerks, an NXP® company, and third-party suppliers. In addition NXP is partnering with third-party vendors to provide integrated systems solutions that include GSM, CDMA, TDMA, and ITU G.7xx speech coders, hybrid echo cancellation, fax, modem, and xDSL software.
Archived content is no longer updated and is made available for historical reference only.
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