i.MX RT500 Crossover MCU with Arm® Cortex®-M33, DSP and GPU Cores

i.MX-RT500

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i.MX RT500 crossover MCUs are part of the EdgeVerse™ edge computing platform and are optimized for low-power HMI applications by combining a graphics engine and a streamlined Cadence® Tensilica® Fusion F1 DSP core with a next-generation Arm® Cortex®-M33 core. These devices are designed to unlock the potential of display-based applications with a secure, power-optimized embedded processor.

i.MX RT500 MCUs are part of the EdgeLock® Assurance program, which offers on-chip security capabilities and is built on a foundation of secure boot, secure debug and a secure life cycle management that is designed to resist remote and software local attacks.

Product Details

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Block Diagram

i.MX RT500 Crossover MCU

i.MX RT500 Crossover MCU
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Features

Cortex-M33 Core Running at a Frequency of up to 275 MHz

  • Arm TrustZone® for asset protection
  • Cortex-M33 built-in memory protection unit (MPU) supporting eight regions
  • Two coprocessors for the Cortex-M33
    • PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
    • CASPER crypto coprocessor to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly Optimized Cadence® Tensilica® Fusion F1 DSP Processor Core Running at Frequencies of up to 275 MHz

  • Hardware floating point unit; single-precision IEEE floating point MAC per cycle

On-Chip Memory

  • Up to 5 MB of system SRAM accessible by both CPUs and all DMA engines
  • 2 x 32 kB FlexSPI cache

Security Features

  • Secure isolation: secure execution environment through Arm® TrustZone® technology for ARMv8-M, symmetric key isolation through hardware engines
  • Secure boot supports implemented in boot ROM, providing immutable root of trust
  • Secure storage: physically unclonable function (PUF) based key store, on-the-fly AES decryption (OTFAD) of off-chip flash for code storage
  • Secure debug: certificate-based debug authentication mechanism
  • Secure update supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
  • Hardware cryptography accelerators:
    • Symmetric cryptography (AES) with 256-bit key strength
    • Asymmetric cryptography acceleration
    • TRNG with 256-bit entropy
    • Hash engine with SHA-256 and SHA-1
  • Secure identity: 128-bit universal unique identifier (UUID) and 256-bit compound device identifier (CDI)
  • A member of the EdgeLock Assurance program, providing on-chip security capabilities.

Graphics

  • 2D GPU with vector graphics acceleration
  • CSI 8/10/16-bit parallel (FlexIO)
  • LCD 8/10/16/18/24-bit parallel (FlexIO)
  • LCD Interface + MIPI DSI

Digital Peripherals

  • Two DMA engines, each with 32 channels
  • Quad/Octal SPI Flash with a dynamic description
  • Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation
  • USB high-speed host/device controller with on-chip PHY
  • Up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI/I2C/I2S/UART
  • One high-speed SPI interface supporting 50 MHz operation
  • Two I3C bus interfaces
  • A digital microphone interface supporting up to 8 channels

Product Program

EdgeLock® Assurance

The i.MX RT500 crossover MCU, part of the EdgeLock Assurance program, is designed to meet industry standards and follows NXP's security-by-design approach.

Documentation

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Design Files

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  • Models

    BSDL Files for i.MX RT500

    ZIPRev 1Jul 22, 2021 07:45:0012.7 KBIMXRT500_BSDL
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  • Models

    IBIS Files for i.MX RT500

    ZIPRev 1Jul 22, 2021 13:24:001.8 MBIMXRT500_IBIS
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