Layerscape® Access LA9310 Programmable Baseband Processor

Click over video to play

Block Diagram

Layerscape Access LA9310 Block Diagram

Layerscape Access LA9310 Block Diagram

Features

Core and Memory Complex

  • One VSPA generation 2, 16AU DSP at up to 614MHz (~80 GFLOP)
  • One M4 32b Arm® core at up to 307MHz

Connectivity and I/O

  • One PCIe Gen3 lane
  • Five {I+Q} ADCs, each sampling at up to 153M samples per second
  • One {I+Q} DAC, sampling at up to 153M samples per second

Acceleration

  • Forward error correction for proprietary communication protocols
  • DMA for internal and host side data movement

Low speed I/O and RFIC control

  • General purpose single lane SPI with four Chip Selects
  • Lightweight LVDS Communication Protocol for RFIC Interface
  • I²C controller
  • UART
  • JTAG

Device

  • 8mm x 8mm package
  • 1.5W total max power at 105C

Buy/Parametrics










































































































Documentation

Quick reference to our documentation types

10 documents

Compact List

Application Note (4)
Data Sheet (1)
Fact Sheet (2)
Product Brief (1)
Reference Manual (1)
Supporting Information (1)

Design Files

Hardware

Quick reference to our board types.

1 hardware offering

Software

Quick reference to our software types.

3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 12 engineering services

Show All

To find additional partner offerings that support this product, visit our Partner Marketplace.

Support

What do you need help with?