Ara-1: Discrete NPU for Optimized Edge-AI

  • This page contains information on a product not recommended for new designs. Specifications and information herein are subject to change without notice. For additional information, please contact NXP support or your NXP sales representative.

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Block Diagram

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NXP Applications Processor and Ara DNPU Connection

ARA-1-DNPU-BD-2

Integration of Ara DNPU and Applications Processors Host with Drivers

ARA-1-DNPU-BD-3

Machine learning deployment flow

ARA-1-DNPU-BD

Features

AI-Model Frameworks Support

  • TensorFlow
  • PyTorch
  • ONNX

AI Model Architectures Supported

  • Convolutional Neural Networks (CNNs)

Performance1

  • Up to 6 equivalent tera operations per second (eTOPS)*

Operating System Support (Runtime)

  • Linux

Interface

  • Peripheral component interconnect express (PCIe) Gen3 x4
  • USB 3.2 Gen 1 x1

Chip Package

  • 15 mm x 15 mm exposed heat sink-flip-chip ball grid array (EHS-FCBGA)

Documentation

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1 documents

Compact List

Design Resources

Hardware

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2 hardware offerings

Software

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2 software files

Note: For better experience, software downloads are recommended on desktop.

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