Ara-1: Discrete NPU for Optimized Edge-AI

ARA-1-DNPU
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Built around an efficient dataflow architecture, Ara-1 discrete neural processing units (DNPUs) deliver the performance and responsiveness needed for real-time AI computing and decision-making. The Ara-1 enables applications to run multiple AI models with zero-latency context-switching. It supports AI-integrated cameras and embedded systems that demand low-latency operation and greater flexibility to accommodate new model operators.

Block Diagram

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NXP Applications Processor and Ara DNPU Connection

ARA-1-DNPU-BD-2

Integration of Ara DNPU and Applications Processors Host with Drivers

ARA-1-DNPU-BD-3

Machine learning deployment flow

ARA-1-DNPU-BD
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Features

AI-Model Frameworks Support

  • TensorFlow
  • PyTorch
  • ONNX

AI Model Architectures Supported

  • Convolutional Neural Networks (CNNs)

Performance¹

  • Up to 6 equivalent tera operations per second (eTOPS)*

Operating System Support (Runtime)

  • Linux

Interface

  • Peripheral component interconnect express (PCIe) Gen3 x4
  • USB 3.2 Gen 1 x1

Chip Package

  • 15 mm x 15 mm exposed heat sink-flip-chip ball grid array (EHS-FCBGA)

¹Maximum performance based on peak computational throughput of Ara-1 (800 MHz) and Host System. Specification subject to change without notice. Performance may vary depending on system configuration.

*eTOPS = equivalent TOPS

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