Fm+ Parallel Bus to I²C-Bus Controller

PCA9665_PCA9665A

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Block Diagram

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PCA9665_PCA9665A BLOCK DIAGRAM

PCA9665_PCA9665A BLOCK DIAGRAM

Block diagram: PCA9665BS, PCA9665D, PCA9665N, PCA9665PW

Features

Key Features

  • Parallel-bus to I2C-bus protocol converter and interface
  • Both leader and follower functions
  • Multi-leader capability
  • Internal oscillator trimmed to 15 % accuracy reduces external components
  • 1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability
  • I2C-bus general call capability
  • Software reset on parallel bus
  • 68-byte data buffer
  • 5 V tolerant I/Os
  • Standard-mode and Fast-mode I2C-bus capable and compatible with SMBus
  • PCA9665A ‘glitch-free’ restart is suitable for use with buffer drivers

Operating Supply Voltage

  • 2.3 V to 3.6 V

ESD Protection

  • Exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101

Latch-Up Testing

  • Done to JEDEC Standard JESD78, which exceeds 100 mA

Packages

  • PCA9665: SO20, TSSOP20, HVQFN20
  • PCA9665A: TSSOP20

Documentation

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Design Resources

Design Files

2 design files

Hardware

1 hardware offering

Engineering Services

2 engineering services

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