DSP56303: 24-bit General Embedded DSP ARCHIVED

High performance DSP56300 core

• 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock
• Object code compatible with the DSP56000 core
• Highly parallel instruction set
• Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
• 56-bit parallel barrel shifter
• 24-bit or 16-bit arithmetic support under software control
• Position-independent code support
• Addressing modes optimized for DSP applications
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
• On-chip concurrent six-channel DMA controller
• On-chip phase-lock loop (PLL) and clock generator
• On-chip emulation (OnCE) module
• JTAG test access port (TAP)
• Address Tracing mode reflects internal accesses at the external port

On-chip memories

• Program RAM, instruction cache, X data RAM, and Y data RAM size is programmable:

• 192 x 24-bit bootstrap ROM

Off-chip memory expansion

• Data memory expansion to two 256 K x 24-bit word memory spaces
• Program memory expansion to one 256 K x 24-bit word memory space
• External memory expansion port
• Chip select logic requires no additional circuitry to interface to SRAMs and SSRAMs
• On-chip DRAM controller requires no additional circuitry to interface to DRAMs

On-chip peripherals

• 8-bit parallel host interface (HI08), ISA-compatible bus interface, providing a cost-effective solution for applications not requiring the PCI bus
• Two enhanced synchronous serial interfaces (ESSI)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable general-purpose I/O pins (GPIO), depending on which peripherals are enabled

Reduced power dissipation

• Very low power CMOS design
• Wait and Stop low power standby modes
• Fully-static logic, operation frequency down to DC
• Optimized power management circuitry