Multimode, multichannel decoder software functionality
Dolby and/or DTS licensing required.
- Dolby Digital
- PCM
- MPEG®2 5.1
- DTS
Digital audio post-processing capabilities
- Bass management
- Volume management
- Delay management
- Dolby ProLogic
- 3D Virtual surround sound
- Lucasfilm THX5.1
- Soundfield processing
- Equalization
Digital Signal Processing Core
-
120 Million Instructions Per Second (MIPS) with a 120 MHz clock at a nominal
3.3 V
-
Object code compatible with the DSP56000 core with highly parallel
instruction set
- Data Arithmetic Logic Unit (Data ALU)
- Program Control Unit (PCU)
- Direct Memory Access (DMA)
-
Software programmable PLL-based frequency synthesizer for the core clock
-
Hardware debugging support: On-Chip Emulation (OnCE) module, Joint Test
Action Group (JTAG) Test Access Port (TAP), and Address Trace mode
On-Chip Memories
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Modified Harvard architecture allows simultaneous access to program and data
memories
-
Program ROMs that may be factory programmed with data/program provided by
the application developer
- 2K-3=5K x 24 Bit Program RAM
- 30K x 24 Bit Program ROM
- 3.5K-5.5K x 24 Bit X-dataRAM
- 6K x 24 Bit X-data ROM
- 5.5K x 24 Bit Y-data RAM
- 6K x 24 Bit Y-data ROM
- 192 x 24-bit bootstrap ROM
- Various memory switches available
Off-Chip Memory Expansion
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Memory expansion up to 4-256K x 24-bit word memory
for P, X, and Y memory when using SRAM
-
Memory expansion up to 4-16M x 24-bit word memory
for P, X, and Y memory when using DRAM
-
Twenty-four data pin external memory expansion port (for high speed external
memory access allowing for a large number of external accesses per sample)
- Chip Select Logic for glueless interface to SRAMs
- On-chip DRAM Controller for glueless interface to DRAMs
Peripheral and Support Circuits
-
Enhanced Serial Audio Interface (ESAI) includes:
-
6 serial data lines, 4 selectable as receive or transmitt and 2
transmitt only.
- capability
- I2S, Sony, AC97, and other audio protocol implementations
- Asynchronous and synchronous operation
-
Serial Host Interface (SHI) features:
- SPI and I2C protocols
- Ten-word receive FIFO
- Support for 8, 16, and 24-bit words
- Byte-wide parallel Host Interface (HDI08) with DMA support
-
Digital Audio Transmitter (DAX): 1 serial transmitter capable of
supporting S/PDIF, IEC958, IEC1937, CP-340, and AES/EBU digital audio
formats
-
Byte-wide, double-buffered parallel port that can be connected directly to
the data bus of a host processor (Host Interface).
- Triple Timer module
- On-chip peripheral registers memory mapped in data memory space
Reduced Power Dissipation
- Very low power (3.3 V) CMOS design
- Wait and Stop low-power standby modes
- Fully-static logic, operation frequency down to 0 Hz (DC)
- Optimized power management circuitry
Package
- 144-pin plastic Thin Quad Flat Pack (LQFP) surface-mount package
DSPAUDIOEVM:DSPAUDIOEVM Evaluation Module