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The MPC8568E PowerQUICC® III family is designed to address the increasing performance requirements for broadband access equipment including 3G/WiMAX/LTE base stations, RNCs, gateways and ATM/TDM/IP equipment. The MPC8568E enables both IP and multi-protocol solutions, combining a high-performance e500 processor core built on Power Architecture® technology scaling up to 1.33 GHz, a flexible communications engine and high-speed system interfaces, enabling customers to handle many functions in a single-chip solution that otherwise would require multiple devices. This high level of integration provides savings in cost, power and board space.
The MPC8568E provides multiprotocol support for both protocol termination and interworking for a wide range of communication protocols, including ATM, POS, ethernet, PPP, HDLC and TDM—allowing the flexibility necessary for broadband access devices. Two enhanced Gigabit Ethernet (GbE) ports, PCI Express® and Serial RapidIO® interconnect technology, enable high-speed links to industrywide switches, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs) and digital signal processors (DSPs). An integrated security engine supports common encryption algorithms, including the Kasumi algorithm needed for 3G wireless security.
MPC8568E Processors
The MPC8568E family consists of the MPC8568E and the MPC8567E. Both are offered in a 1023-pin FC-BGA package for pin compatibility.
MPC8568E PROCESSOR HIGHLIGHTS
|
| |
MPC8568E |
MPC8567E |
| Core |
e500 |
e500 |
| CPU Speed |
1.0, 1.2, 1.33 GHz |
800 MHz, 1.0, 1.2, 1.33 GHz |
| L1 I/D Cache (KB) |
32 |
32 |
| L2 Cache (KB) |
512 |
512 |
| Memory Controller |
64-bit DDR/DDR2 |
64-bit DDR/DDR2 |
| Local Bus |
32-bit |
32-bit |
| System Interfaces |
sRIO, PCI, PCI Express® (x8) |
sRIO, PCI, PCI Express® (x4) |
| Stand-Alone 10/100/1000 Ethernet |
2 (eTSEC) |
-- |
| Table Lookup Unit (TLU) |
Yes |
No |
| QUICC Engine™ |
Up to 533 MHz |
Up to 533 MHz |
| Ethernet |
3 x Gigabit, 8 x 10/100 |
3 x Gigabit, 8 x 10/100 |
| ATM (AAL0,1,2,5) |
2 x UTOPIA-L2, 124 M-PHY |
2 x UTOPIA-L2, 124 M-PHY |
| Packet over SONET (POS) |
2 x POSPHY-L2 |
2 x POSPHY-L2 |
| 8 TDMs (256 channels of HDLC) |
8 x T1/E1, 2 x T3/E3 |
8 x T1/E1, 2 x T3/E3 |
| Protocol Interworking |
Yes |
Yes |
| Security Engine |
SEC 2.4 |
SEC 2.4 |
| Additional Interfaces |
DUART, 2 x I2C, 2 x SPI |
DUART, 2 x I2C, 2 x SPI |
| Interrupt Controller |
Yes |
Yes |
| Package |
1023 FC-BGA |
1023 FC-BGA |
Key Advantages
- High level of integration and performance, simplifying board design
- Consistent programming model across the PowerQUICC III family of processors
- Flexible system-on-chip (SoC) platform can help improve time to market
- 90 nm silicon-on-insulator (SOI) technology
- High-performance enhanced e500 core
- 512 KB L2 cache
- High internal processing bandwidth
- Integrated DDR/DDR2 memory controller
- Two integrated triple speed Ethernet controllers (enhanced TSEC)
- Advanced QUICC Engine® technology supports a wide range of protocols and associated interworking
- TLU provides off-load for table search functions associated with IP forwarding, firewall and access control list (ACL) applications
- Flexible high-speed interconnect interfaces:
- Serial RapidIO® interconnect technology
- PCI Express® support
- PCI and local bus interface support
- Integrated security engine
Access to the errata document for this device requires an NDA. Contact your local NXP® Sales Office or NXP Authorized Distributor.
