MPC850: PowerQUICC^® Processor with CPM (2 SCC, 2 SMC), 10T Ethernet

Embedded MPC8xx Core with 87 MIPS at 66 MHz (using Dhrystone 2.1)

• 2-Kbyte Instruction Cache
• 1-Kbyte Data Cache
• Instruction and Data MMUs
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
• 26 External Address Lines
• Complete Static Design (0-66 MHz Operation)
• Memory Controller (Eight Banks)
• General-Purpose Timers
• System Integration Unit (SIU)
• Interrupts
• Communications Processor Module (CPM)
• Four Baud Rate Generators
• Up to two SCCs (Serial Communication Controller with Ethernet Support)
• One USB Port
• Two SMCs (Serial Management Channels)
• One SPI (Serial Peripheral Interface)
• One I²C (Inter-Integrated Circuit) Port
• Time-Slot Assigner
• Parallel I/O Ports (supports UTOPIA)
• PCMCIA Interface
• Low Power Support
• Debug Interface
• 3.3 V Operation
• 3.3 V System Bus Operation
• 256-Pin Ball Grid Array (BGA)