MPC850: PowerQUICC^® Processor with CPM (2 SCC, 2 SMC), 10T Ethernet

Overview

The MPC850 PowerQUICC^® processor offers a versatile, integrated, low-cost solution for variety of controller, networking, and communications applications.

Includes extensive communications and system integration support
Simplifies development and accelerates time-to-market
Offloads core tasks for increased performance and efficiency
Backed by strong third-party tool support through Our Design Alliance Program

MoreLess

Features

Embedded MPC8xx Core with 87 MIPS at 66 MHz (using Dhrystone 2.1)

2-Kbyte Instruction Cache
1-Kbyte Data Cache
Instruction and Data MMUs
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
26 External Address Lines
Complete Static Design (0-66 MHz Operation)
Memory Controller (Eight Banks)
General-Purpose Timers
System Integration Unit (SIU)
Interrupts
Communications Processor Module (CPM)
Four Baud Rate Generators
Up to two SCCs (Serial Communication Controller with Ethernet Support)
One USB Port
Two SMCs (Serial Management Channels)
One SPI (Serial Peripheral Interface)
One I²C (Inter-Integrated Circuit) Port
Time-Slot Assigner
Parallel I/O Ports (supports UTOPIA)
PCMCIA Interface
Low Power Support
Debug Interface
3.3 V Operation
3.3 V System Bus Operation
256-Pin Ball Grid Array (BGA)

MoreLess

Features

Embedded MPC8xx Core with 87 MIPS at 66 MHz (using Dhrystone 2.1)

2-Kbyte Instruction Cache
1-Kbyte Data Cache
Instruction and Data MMUs
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
26 External Address Lines
Complete Static Design (0-66 MHz Operation)
Memory Controller (Eight Banks)
General-Purpose Timers
System Integration Unit (SIU)
Interrupts
Communications Processor Module (CPM)
Four Baud Rate Generators
Up to two SCCs (Serial Communication Controller with Ethernet Support)
One USB Port
Two SMCs (Serial Management Channels)
One SPI (Serial Peripheral Interface)
One I²C (Inter-Integrated Circuit) Port
Time-Slot Assigner
Parallel I/O Ports (supports UTOPIA)
PCMCIA Interface
Low Power Support
Debug Interface
3.3 V Operation
3.3 V System Bus Operation
256-Pin Ball Grid Array (BGA)

Data Sheets

Application Notes

Previous Next

Comparison Table

MPC850 Family Members

	MPC850	MPC850DE	MPC850SR	MPC850DSL
64-Channel HDLC Support	-	-	Yes	No
Number of SCCs	1	2	2	2
Ethernet Support	Yes	Yes	Yes	Yes
ATM	-	-	Yes	Yes

MPC850 Integrated Communication Controller Mask Set

	Qual	Process	Mask	IMMR [16:31]
Rev B	XC	.32µ TLM	4H97G	2101
Rev A	XC	.32µ TLM	2H89G	2100
Rev 0	XC	.42µ TLM	6F98S	2002

xx denotes family variants including standard 850, DE, SR, and DSL.
nn denotes speed grade. Please contact your local NXP Sales Office or Distributor for exact speeds available.

MPC850: PowerQUICC® Processor with CPM (2 SCC, 2 SMC), 10T Ethernet

Overview

Features

Comparison Table

MPC850 Family Members

MPC850 Integrated Communication Controller Mask Set

MPC850: PowerQUICC^® Processor with CPM (2 SCC, 2 SMC), 10T Ethernet