PowerQUICC® Processor with CPM (2 SCC, 2 SMC), 10T Ethernet

  • This page contains information on a product that is not recommended for new designs.

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Block Diagram



  • 2-Kbyte Instruction Cache
  • 1-Kbyte Data Cache
  • Instruction and Data MMUs
  • Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
  • 26 External Address Lines
  • Complete Static Design (0-66 MHz Operation)
  • Memory Controller (Eight Banks)
  • General-Purpose Timers
  • System Integration Unit (SIU)
  • Interrupts
  • Communications Processor Module (CPM)
  • Four Baud Rate Generators
  • Up to two SCCs (Serial Communication Controller with Ethernet Support)
  • One USB Port
  • Two SMCs (Serial Management Channels)
  • One SPI (Serial Peripheral Interface)
  • One I2C (Inter-Integrated Circuit) Port
  • Time-Slot Assigner
  • Parallel I/O Ports (supports UTOPIA)
  • PCMCIA Interface
  • Low Power Support
  • Debug Interface
  • 3.3 V Operation
  • 3.3 V System Bus Operation
  • 256-Pin Ball Grid Array (BGA)

Part numbers include: MPC850CVR50BU, MPC850CZQ50BU, MPC850DECVR66BU, MPC850DEZQ50BU, MPC850DSLCZQ50BU, MPC850SRVR50BU, MPC850SRVR80BU, MPC850VR50BU.

Comparison Table

MPC850 Family Members

HDLC Support
- - Yes No
Number of SCCs 1 2 2 2
Ethernet Support Yes Yes Yes Yes
ATM - - Yes Yes

MPC850 Integrated Communication Controller Mask Set

Part Numbers Qual Process Mask IMMR [16:31]
Rev B XC .32µ TLM 4H97G 2101
Rev A XC .32µ TLM 2H89G 2100
Rev 0 XC .42µ TLM 6F98S 2002

xx denotes family variants including standard 850, DE, SR, and DSL.
nn denotes speed grade. Please contact your local NXP Sales Office or Distributor for exact speeds available.


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Note: For better experience, software downloads are recommended on desktop.


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