S32N55 Vehicle Super-Integration Processor

  • Preproduction
  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

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Block Diagram

S32N55 Product Features

S32N55 Block Diagram

Features

Processors

  • 16x split-lock Arm® Cortex®-R52 cores operating at up to 1.2 GHz
  • Arm Neon™ Single Instruction Multiple Data (SIMD) technology
  • Lockstep Arm® Cortex®-M7 System Manager
  • Lockstep Arm Cortex-M7 Communication Manager

Memory

  • 48 MB Platform SRAM, 3 MB System Memory SRAM and 4 MB L2 Cache SRAM
  • 2x channel NVM interface supporting serial, quad and octal NOR memory
  • eMMC 5.1 NAND flash and SD Card/SDIO flash support
  • LPDDR4X flash and LPDDR4X/5/5X DRAM interfaces for memory expansion

Real-Time Applications Integration

  • Full on-chip hardware isolation and virtualization for isolated, mixed-criticality applications
  • Core-to-pin virtual hardware isolation technology supports freedom from interference

Functional Safety

  • System manager, consisting of a lockstep Cortex-M7 processor core, manages functional safety
  • Hardware provides freedom from interference and virtualized Quality of Service (QoS) mechanisms for shared resources
    • Keeps fault impact at the integrated ECU level with local reactions
    • Runtime operating mode, safe stop and reset all controlled individually for each integrated ECU, reducing the number of faults that lead to SoC reset
  • Processor developed according to processes that are certified to ISO 26262 for ASIL D functional safety

Security

  • Integrated hardware security engine (HSE2) for Root of Trust (RoT)
    • Secure boot, security services and key management
  • Public key infrastructure and side-channel attack resistance
  • Distributed security approach to provide increased availability of security services, increased parallelism of security operations, clearer prioritization between tasks and minimizes latency
  • Developed according to cybersecurity processes that are certified to ISO/SAE 21434, UN R155 and also targeted for SESIP Level 2 certification

Communications and Networking

  • Lockstep Arm Cortex-M7 to manage communication traffic
  • CAN Hub virtualizes CAN I/O and allows applications to share the same CAN I/O pins, allows CAN frames to be routed to multiple FlexCAN controllers and offloads CAN-to-CAN routing from the host core
  • 24x CAN FD, 4x CAN XL, 10x LIN and 1x 2-ch FlexRay® interfaces
  • Integrated dual-port Time-Sensitive Networking (TSN) Gigabit Ethernet switch
  • 2x Ethernet MACs each operating from 10 Mbit/s to 2.5 Gbit/s and supporting MII / RMII / RGMII / SGMII / OC-SGMII
  • PCI Express Gen 4 (Root Complex) x1/x2

Documentation

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1 documents

Hardware

4 hardware offerings

Software

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Engineering Services

5 engineering services

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Training

1 trainings